Kousuke Okuyama

Hot carrier degradation modes and optimization of LDD MOSFETs

The hot carrier instability and the related device characteristics of Leff= 1µm MOSFETs with Lightly Doped Drain (LDD) structure is evaluated in detail. For the n- dose below 1E13/cm2, a new type of IBB and IG increase was found when the gate bias, VG, was increased toward and over the drain bias, VD, and related new modes of hot carrier instability were confirmed. The instability for the lower VG stress is attributed to the charge build-up at the n- drain region, while the instability for the larger VG stress is attributed to the oxide degradation at both source and drain regions. The device characteristics and the mechanism of instability for n→= 1E13/cm2 are similar to those of conventional devices. It is shown that the instability inherent to the LDD structure can be suppressed by optimizing the n-dose. Thereby, it is important that the lateral electric field peak remains under the gate.

Water-related threshold voltage instability of polysilicon TFTs

Negative bias-temperature (NBT) instability of polysilicon thin film transistors (TFTs) has been studied. We found water is strongly related to this phenomenon and can result in a threshold voltage shift of 1 V or more within a short time under NBT stress. This paper shows the results supporting this fact and proves, by using thin LPCVD SiN films, the suppression of water penetration and/or content in the oxides is essential in reducing this instability to an acceptable level. A qualitative model is presented to explain the role of water and experimental results.<<ETX>>

Monte Carlo simulation of stress-induced leakage current by hopping conduction via multi-traps in oxide

For the first time a new simulation method applicable to a stress-induced leakage current (SILC) by successive hopping conduction via multi-traps is presented. This method describes the electron hopping process and trap distribution microscopically. A rate-limiting process of hopping conduction is found to be an electrode-to-trap tunneling, which causes large electric field and temperature dependences of the current.

Repair yield simulation with iterative critical area analysis for different types of failure

We propose a general method for repair yield estimation based on critical area analysis using a commercial Monte-Carlo simulator. We classify failures into several types according to the repair rules and use iterative critical area analysis for each type of failure (ICAA-ETF) to calculate the repair yield. Our proposed method makes it possible to accurately estimate within a few hours the repair yield of a memory product. An example of application to an actual SRAM product is discussed to illustrate in detail how our method can be used for critical area calculation and repair yield modeling.

Degradation of I/O devices due to ESD-induced dislocations

Degradation in leakage current characteristics of I/O circuits due to ESD events has been studied. TEM observations revealed the generation of crystalline defects in the silicon substrate such as dislocations induced by ESD stress which increased the reverse leakage current level of the p-n junctions in the I/O circuits. We found that current crowding occurs in the silicon surface region during an ESD event resulting in defect generation. We also show that optimal impurity profiles for protection devices can avoid such current crowding and hence the leakage current degradation.<<ETX>>

Statistical BSIM3 model parameter extraction and fast/slow model parameter determination for high speed SRAM parametric yield estimation

To achieve high yield without degrading performance, it is important to consider process variations during circuit designing. There is also a strong need of good model parameters for fast/slow cases, which represent the performance variations. We have developed a statistical model parameter extraction method, to extract sets of process related BSIM3 parameters from in-line measurement data such as drain saturation current and threshold voltage. This extraction method is based on our pre-silicon parameter generation methodology, which makes the model parameter predictable when changing some parameters related to the process. We have also proposed a method to determine the fast/slow model parameters using the statistical model parameters, for circuit designing. We have applied this method to a 0.20 /spl mu/m process SRAM test chip, and have obtained good results comparing to measurement, thus making it possible to estimate parametric yield by simulation.

Detailed observation of small leak current in flash memories with thin tunnel oxides

This paper describes a method for measuring the small current through the oxides on the order of 10/sup -20/ A or less using a floating gate MOSFET and the application results on flash memories with thin tunnel oxides. The method is based on accurate measurement of the threshold voltage of a floating gate MOSFET with no charge in the floating gate. We applied the method to flash memories to investigate the leakage current behaviour through thin tunnel oxides with very small areas (<0.16 /spl mu/m/sup 2/), and found some anomalous phenomena which cannot be obtained from stress-induced leakage current (SILC) measurements using large capacitors. We also discuss possible mechanisms to explain the phenomena.

A highly manufacturable 0.18 /spl mu/m generation logic technology

A 0.18 /spl mu/m generation logic technology has been developed with 0.14 /spl mu/m gate length transistors. Guidelines to suppress mechanical stress in shallow trench isolation are clearly described. Stable Co salicide process has been integrated with the combination of NO treated gate oxide and BF/sub 2/ source drain ion implantation. Amorphous Si with RTA is the key to control grain size and suppress large variation of drain current in small size transistors. Two kinds of metallization systems, aluminum with SiOF dielectrics and dual damascene Cu are developed in the same layout rule.

Anomalous Leakage Current Model for Retention Failure in Flash Memories

l. Introduction Oxide reliability is always one of the most crucial issues in flash memories. Although SILC (Stress-Induced Leakage Current) is now widely recognized, a retention lifetime of a megabit-scale memory is determined by a very small number of failure bits showing an anomalously large SILC tl-31. However no models for the retention lifetime of failure bits have been established yet. In this paper, for the first time, we develop a quantitative model for this anomalous SILC arid investigate the properties of retention lifetime of failure bits.

Effects of process-induced mechanical stress on ESD performance

We studied the generation of dislocations during an ESD event by electrothermal and mechanical stress simulations based on analysis of critical mechanical stress for defect formation. We found the local thermal stress by ESD generates dislocations cooperatively with the residual mechanical stress in the Si substrate due to field oxidation. This means that process-induced mechanical stress is another key factor for controlling ESD performance, which will be important especially in low-power applications with severe leak requirements.