Katsumasa Watanabe

Waiting false path analysis of sequential logic circuits for performance optimization

The paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. The paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

A New Approach to Online FPGA Placement

In a partially reconfigurable FPGA, arbitrary portions of its logic resources and interconnection networks can be reconfigured without affecting the other parts. Thus, several tasks can be mapped and executed concurrently in the FPGA. In order to execute the tasks efficiently using the limited resources of the FPGA, resource management becomes very important. Although some online FPGA placement methods have, recently, been proposed, they cannot handle I/O communications of the tasks. Taking such I/O communications into consideration, we introduce a new approach to online FPGA placement. We present a task placement algorithm which uses I/O routing information of each empty area to select a suitable area for each task. The algorithm uses a combination of two new fitting strategies and modified versions of two existing strategies.

Speech recognition chip for monosyllables

In the paper, we present a real-time speech recognition chip for monosyllables such as A, B, ..., etc. The chip recognizes up to 64 monosyllables based on the Hidden Markov Model (HMM), which is a well known speaker-independent recognition method. The chip accepts a short-speech frame including 256 16-bit digitized samples corresponding to 11.6 msec period, and outputs the 6-bit symbol code of monosyllables for 16 short-frames (corresponding to 185.6 msec). A learning circuit to update HMM parameters for the recognition chip has also been designed, and the recognition chip includes an interface to the learning circuit. We have fabricated the recognition chip by VDEC Rohm 0.6 um process on a 4.5 mm x 4.5 mm chip. We have also made a layout of the entire circuit including the learning circuit by VDEC Rohm 0.35 um process on a 4.9 mm x 4.9 mm chip.

Multi-clock path analysis using propositional satisfiability

We present a satisfiability based multi-clock path analysis method. The method uses propositional satisfiability (SAT) in the detection of multi-clock paths. We show a method to reduce the multi-clock path detection problems to SAT problems. We also show heuristics on the conversion from multi-level circuits into CNF formulae. We have applied our method to ISCAS89 benchmarks and other sample circuits. Experimental results show the improvement on the manipulatable size of circuits by using SAT.

An application specific Java processor with reconfigurabilities

The paper presents an application specific Java processor including reconfigurabilities, which is a DLX like pipeline processor with 5 stages and executes Java byte codes directly. Reconfigurabilities are the key technologies for application specific operations. We have introduced two reconfigurabilities: (1) a mechanism to override the control signals for a specific instruction, (2) external components can be attached with the same input and output ports as the internal ALU.

Robust quantum algorithms with ε-biased oracles

This paper considers the quantum query complexity of e-biased oracles that return the correct value with probability only 1/2 + e. In particular, we show a quantum algorithm to compute N-bit OR functions with

An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs

O(\sqrt{N}/{\varepsilon})

A real-time 64-monosyllable recognition LSI with learning mechanism

queries to e-biased oracles. This improves the known upper bound of

Robust Quantum Algorithms Computing OR with ε-Biased Oracles

O(\sqrt{N}/{\varepsilon}^2)

Event-oriented computing with reconfigurable platform

and matches the known lower bound; we answer the conjecture raised by the paper [1] affirmatively. We also show a quantum algorithm to cope with the situation in which we have no knowledge about the value of e. This contrasts with the corresponding classical situation, where it is almost hopeless to achieve more than a constant success probability without knowing the value of e.