Katsumi Hisano

Thermal management estimations for buried bump interconnection technology printed wiring boards with bump (filled via) interconnection

We have developed B/sup 2/it (buried bump interconnection technology) printed wiring boards (PWBs) for high density and high performance requirements. Semiconductor devices are attaining higher operating speeds and higher integration, and PWBs thus require improved thermal management properties. Conventional PWBs have low thermal conductivity compared with ceramic substrates, etc. The B/sup 2/it PWBs have filled via holes using Ag paste bumps to connect wiring lines between neighbouring layers. This feature is different from conventional PWBs with copper-plated through holes. The manufacturing process for B/sup 2/it PWBs is also unique and simple because the bumps are formed by printing and interconnections between layers are formed by lamination without drilling and plating. The filled via holes can become thermal via holes for improved heat radiation. The thermal conductivity of the via hole material is useful for designing the B/sup 2/it PWBs. This paper reports the thermal properties of the B/sup 2/it PWBs by measuring the thermal resistance of various filled via hole samples. The thermal resistance was calculated from measurement of the temperature difference between the sample surfaces using an original measurement system, and the thermal conductivity of the via hole material was simulated from the measured values. As a result, the thermal conductivity of the via hole material was found to be very high compared with that of the normal printed Ag paste, and the B/sup 2/it PWBs had thermal management properties which were good enough for high density packaging.

Development of sheet type thermal conductive compound using AlN

The conventional sheet type thermal conductive compound is processed by uniformly mixing high thermal conductivity materials into the organic resin. However, it is difficult to raise the sheet thermal conductivity using this compound, due to the fact that the organic resin lies between materials of high thermal conductivity. In order to solve the above-mentioned problem, the authors developed a new type of thermal sheet having thermal conductivity above 20 W/m.k, as measured with a steady state thermal conductivity meter. The proposed sheet type thermal conductive compound was formed by penetrating finely processed aluminum nitride ceramic, which was arranged uniformly, on both sides of the organic resin sheet (thermal hardening silicone). The thermal sheet formed in this way has high thermal conductivity, good electrical insulation property, and flexibility.

A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter

The frequency drift of an open-loop PLL is an issue for direct modulation applications such as Bluetooth transceivers. The drift mainly comes from the temperature variation of the VCO during the TX operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through full-chip thermal analysis. Moreover, a novel temperature-compensated VCO by employing a new biasing scheme is proposed. The combination of these two techniques enables power reduction of the transmitter by 33% without sacrificing performance.

Thermal analysis of notebook personal computer

This paper describes a thermal analysis of a notebook personal computer (PC). A numerical analysis was carried out for the whole domain of the PC, excluding display portion. The numerical model includes Si chips, packages, printed circuit boards (PCBs), casing, etc. In the design of a notebook PC, dead space is kept to a minimum, so the characteristic length for Rayleigh number, which represents the property of the heat transfer between components inside the cabinet is lower than its critical value, and natural convection does not occur inside the PC. Hence, thermal analysis can be performed by heat conduction analysis. To reduce computational load, thermal analysis was divided in two stages and calculation was performed on an EWS. Measured and calculated temperature rise of the electronic parts showed good agreement. This led to the conclusion that the present thermal analysis method can be a useful tool for the design of notebook PCs.

Health-monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Health monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Improvement of Heat Transfer Performance of Loop Heat Pipe for Electronic Devices

In this paper is presented the results on performance of the cooling model using Loop Heat Pipe (LHP) system. In recent years, ever-ending demand of high performance CPU led to a rapid increase in the amount of heat dissipation. Consequently, thermal designing of electronic devices need to consider some suitable approach to achieve high cooling performance in limited space. Heat Pipe concept is expected to serve as an effective cooling system for laptop PC, however, it suffered from some problems as follows. The heat transport capability of conventional Heat Pipe decreases with the reduction in its diameter or increase in its length. Therefore, in order to use it as cooling system for future electronic devices, the above-mentioned limitations need to be removed. Because of the operating principle, the LHP system is capable of transferring larger amount of heat than conventional heat pipes. However, most of the LHP systems suffered from some problems like the necessity of installing check valves and reservoirs to avoid occurrence of counter flow. Therefore, we developed a simple LHP system to install it on electronic devices. Under the present experimental condition (the working fluid was water), by keeping the inside diameter of liquid and vapor line equal to 2mm, and the distance between evaporator and condenser equal to 200mm, it was possible to transport more than 85W of thermal energy. The thickness of evaporator was about 5mm although it included a structure to serve the purpose of controlling vapor flow direction inside it. Successful operation of this system at inclined position and its restart capability are confirmed experimentally. In order to make the internal water location visible, the present LHP system is reconstructed using transparent material. In addition, to estimate the limit of heat transport capability of the present LHP system using this thin evaporator, the air cooling system is replaced by liquid cooling one for condensing device. Then this transparent LHP system could transport more than 100W of thermal energy. However, the growth of bubbles in the reserve area with the increase in heat load observed experimentally led to an understanding that in order to achieve stable operation of the LHP system under high heat load condition, it is very much essential to keep enough water in the reserve area and avoid blocking the inlet with bubbles formation.Copyright

Health monitoring method for load assessment in reliability design of printed circuit board

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the maintenance, the reliability design method and the availability in improper use conditions of electronic equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards by use of a hierarchical Bayes model based on CAE results of stress simulation and experiment data from actual measurements. We applied this method to note PC. It is confirmed that this method can estimate the structural response index distribution of the printed circuit board from monitoring variables, and that the statistical load assessment concerning cyclic load and the maximum load distribution can be conducted.

Coupled Thermal-Stress Analysis for FC-BGA Packaging Reliability Design

In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stress distributions of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distributions. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a flip-chip ball grid array package under field conditions. It was found that: 1) the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to the average contact thermal resistance in the case of uniform contact pressure, and 2) the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation under field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design. It was found that the sensitivity of uncertain variables and the thermal fatigue life distribution of solder joints could change significantly depending on a combination of factors concerning the failure sites of solder bumps and the boundary conditions of the motherboard.

A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters

A frequency drift of open-loop PLL is an issue for the direct-modulation applications such as Bluetooth transceiver. The drift mainly comes from a temperature variation of VCO during the transmission operation. In this paper, we propose the optimum location of the VCO, considering the temperature gradient through the whole-chip thermal analysis. Moreover, a novel temperature-compensated VCO, employing a new biasing scheme, is proposed. The combination of these two techniques enables the power reduction of the transmitter by 33% without sacrificing the performance.