Kenji Hirohata

Mechanical fatigue test method for chip/underfill delamination in flip-chip packages

Underfill resin between Si chips and printed circuit boards is useful for improving the reliability of flip-chip packages. Generally, thermal cycle tests (TCTs) are applied to electronic packages under development in order to prove their reliability. At the early stage of development, however, a more effective test method is desirable, because TCTs are time-consuming. A new mechanical fatigue test for the underfill resin in flip-chip packages, namely the four points support test method, is proposed in this paper. The validity of the mechanical test method could be verified from the results of stress analyses and experiments. Considering the chip/underfill delamination statistically based on the assumption of Markov process, it was shown that the delamination probability during cyclic loads could be estimated with equations of the displacement range and number of cycles.

Damage Path Simulation of Solder Joints in QFP

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.Copyright

Health-monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Health monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Effects of Thermal Cycle Conditions on Thermal Fatigue Life of Substrate With Cu Through-Hole

The Cu through-hole is a structure of electroplated Cu thin film, which penetrates the substrate. Because of the mismatch of the thermal expansion coefficient between the Cu thin film and the substrate along the thickness direction, thermal strain occurs repeatedly at the Cu through-hole part with the variation of temperature. As a result, the thermal fatigue failure of Cu through-hole part is one of the failure modes of the substrate. In this study, the effects of thermal cycle conditions on the thermal fatigue life of the substrate with Cu through-hole were investigated by thermal cycle tests and Finite Element Method (FEM)-based analyses. Thermal cycle tests of the substrate with Cu through-hole were conducted under different thermal conditions. The effects of dwell time, temperature range and maximum temperature were investigated. Among these factors, the maximum temperature shows the greatest influence on the thermal fatigue life of Cu through-hole part. FEM-based thermal cycle analyses were also carried out to understand the effects of thermal cycle conditions. The glass cloth structures of the substrate should be considered in the analyses, because their rigid properties probably affect the generation of the failure at the through-hole part. In this study, glass cloth structures were modeled by taking advantage of a homogenization method. On the other hand, the inelastic constitutive model of the electroplated Cu thin film was introduced in the analyses in order to describe the creep deformation during the dwell process of thermal cycles. The inelastic strain range of the Cu through-hole during thermal cycles was calculated from the analysis results and the effectiveness of the Coffin-Manson law was evaluated. The results showed that the fatigue life prediction using the Coffin-Manson model was effective in the range of the same substrate thickness and the same maximum temperature. Additionally the influences of material model and material constants of epoxy resin were investigated to expand the range of application of the fatigue life prediction.Copyright

Fast CT-FFR Analysis Method for the Coronary Artery Based on 4D-CT Image Analysis and Structural and Fluid Analysis

Non invasive fractional flow reserve derived from CT coronary angiography (CT-FFR) has to date been typically performed using the principles of computational fluid analysis in which a lumped parameter coronary vascular bed model is assigned to represent the impedance of the downstream coronary vascular networks absent in the computational domain for each coronary outlet. This approach may have a number of limitations. It may not account for the impact of the myocardial contraction and relaxation during the cardiac cycle, patient-specific boundary conditions for coronary artery outlets and vessel stiffness. We have developed a novel approach based on 4D-CT image tracking (registration) and structural and fluid analysis based on one dimensional mechanical model, to address these issues. In our approach, we analyzed the deformation variation of vessels and the volume variation of vessels to better define boundary conditions and stiffness of vessels. We focused on the blood flow and vessel deformation of coronary arteries and aorta near coronary arteries in the diastolic cardiac phase from 70% to 100 %. The blood flow variation of coronary arteries relates to the deformation of vessels, such as expansion and contraction of the cross-sectional area, during this period where resistance is stable, pressure loss is approximately proportional to flow. We used a statistical estimation method based on a hierarchical Bayes model to integrate 4D-CT measurements and structural and fluid analysis data. Under these analysis conditions, we performed structural and fluid analysis to determine pressure, flow rate and CT-FFR. Furthermore, the reduced-order model based on fluid analysis was studied in order to shorten the computational time for 4D-CT-FFR analysis. The consistency of this method has been verified by a comparison of 4D-CT-FFR analysis results derived from five clinical 4D-CT datasets with invasive measurements of FFR. Additionally, phantom experiments of flexible tubes with and without stenosis using pulsating pumps, flow sensors and pressure sensors were performed. Our results show that the proposed 4D-CT-FFR analysis method has the potential to accurately estimate the effect of coronary artery stenosis on blood flow.Copyright

Large-Scale Damage Path Simulation for Solder Joints in a BGA Package

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.Copyright

Prognostic Health Monitoring Method for Fatigue Failure of Solder Joints on Printed Circuit Boards Based on a Canary Circuit

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.© 2013 ASME

Low cycle fatigue crack initiation and propagation behavior of copper thin films used in electronic devices

This paper presents the crack initiation and propagation behavior in 4-point bending low cycle fatigue for four kinds of copper thin films used in electronic devices at room and 353K. There was a distinct difference in cycles to crack depending on the fabrication process but not on surface roughness. The crack propagation rates depended on the fabrication process of the films but surface roughness. Raising the testing temperature accelealeted cycle to crack and cracks propagation rate.

Prognostic health monitoring method for printed circuit boards subjected to random cyclic loads

For random dynamic loads such as cyclic shock and vibration of semiconductor modules, a method using field load assessment and fatigue life estimation is proposed in order to improve the reliability of electronic products. The evolutionary spectrum method is introduced for random dynamic load modeling. The statistical distribution of structural responses such as the deformation and strain of solder joints and printed circuit boards can be predicted by Monte Carlo simulations based on the finite element method and random dynamic load modeling. A feasibility study of the failure probability estimation method is conducted for application to a printed circuit board on which a flip-chip ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint failure.