Minoru Mukai

Mechanical fatigue test method for chip/underfill delamination in flip-chip packages

Underfill resin between Si chips and printed circuit boards is useful for improving the reliability of flip-chip packages. Generally, thermal cycle tests (TCTs) are applied to electronic packages under development in order to prove their reliability. At the early stage of development, however, a more effective test method is desirable, because TCTs are time-consuming. A new mechanical fatigue test for the underfill resin in flip-chip packages, namely the four points support test method, is proposed in this paper. The validity of the mechanical test method could be verified from the results of stress analyses and experiments. Considering the chip/underfill delamination statistically based on the assumption of Markov process, it was shown that the delamination probability during cyclic loads could be estimated with equations of the displacement range and number of cycles.

Damage Path Simulation of Solder Joints in QFP

Fatigue life prediction of solder joints is one of the most important areas of research in the development of reliable electronic packages. Recent trends in electronic package development indicate a shift toward smaller solder joints and larger package sizes, and temperature changes under field conditions are also becoming greater. Since reliability design of solder joints has become severer, the estimation of the crack propagation is becoming important like the estimation of the crack initiation. In the present study, a new method of estimating the crack propagation, which is based on finite element analysis without geometrical crack model, was examined, in order to ensure suitability for practical use in electronic package design. On the basis of a damage model assumed for Sn-37Pb solder, the new method called ‘damage path simulation’ was verified for solder joints in QFP (Quad Flat Package). In the case of solder joints of the gull-wing type, fatigue cracks are commonly initiated from the upper surface of the solder fillet, and propagated in the vicinity of the interface with the outer lead. It was clear that the extension of the damage path showed good agreement with the behavior of crack propagation observed in the actual thermal cycle tests. Damage path extension from a pointed end of outer lead is also simulated simultaneously with that from the upper surface of the solder fillet, and both damage paths were finally combined at a gap between outer lead and printed circuit board. The advantage of the present method is especially evident when the fatigue cracks were initiated from two or more regions. From the results of this study, it was concluded that the estimation of the crack propagation in solder joints based on the present method is satisfactory for engineering purposes.Copyright

Coupled Thermal-Stress Analysis for FC-BGA Packaging Reliability Design

In order to improve electronics packaging design, it is important to evaluate the cooling performance and reliability of the electronics packaging structure of a product. To that end, it is necessary to predict the temperature, deformation, and stress distributions of the package under field conditions. In the case of a packaging structure comprising a flip-chip ball grid array package, a heat spreader, thermal grease, a cooling structure, solder joints, and a motherboard, an increase in the contact thermal resistance may occur, depending on the interface contact condition between the cooling structure and the heat-spreader due to the thermal deformation of the package. Contact thermal resistance problems involve the interactive relationship of the thermal and stress distributions. A coupled thermal-stress analysis, with consideration of the time-space variation of contact thermal resistance, was conducted to duplicate the behavior of temperature, deformation, and stress distributions of a flip-chip ball grid array package under field conditions. It was found that: 1) the average contact thermal resistance across the interface between the heat-spreader and the plate fin, which was predicted by the coupled thermal-stress analysis, increased compared to the average contact thermal resistance in the case of uniform contact pressure, and 2) the contact thermal resistance will vary depending on the deformation mode, such as convex upward and downward, due to heat dissipation under field conditions. In addition, a reliability prediction method for thermal fatigue failure of solder bumps based on coupled thermal-stress analysis and statistical and probabilistic methods was proposed in order to select a suitable packaging solution at an early stage of design. It was found that the sensitivity of uncertain variables and the thermal fatigue life distribution of solder joints could change significantly depending on a combination of factors concerning the failure sites of solder bumps and the boundary conditions of the motherboard.

Health-monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Health monitoring method of note PC for cooling performance degradation and load assessment

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the effective maintenance, the reliability design method and the availability in the improper use conditions of digital equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards in digital equipment by use of a hierarchical Bayes model based on CAE (Computer Aided Engineering) results of thermal stress simulation and experiment data from actual measurements. We applied this method to note PC that can monitor the device load factor and revolution number of cooling fan. It is shown that this method can estimate the temperature and deformation distribution of the printed circuit board from monitoring variables through latent variables such as thermal dissipation of the device and thermal boundary condition by use of the hierarchical Bayes model. And it is confirmed that the statistical load assessment concerning thermal cyclic load and the maximum load distribution can be conducted using the estimated temperature and deformation data. Furthermore, we verified that the cooling performance degradation can be assessed, if the temperature difference per unit thermal value between two suitable points on the printed circuit board can be obtained. It is concluded that the proposed method can be effective to assess the thermal load history and cooling performance degradation.

Large-Scale Damage Path Simulation for Solder Joints in a BGA Package

There is high demand for fatigue life prediction of solder joints in electronic packages such as ball grid arrays (BGAs). A key component of fatigue life prediction technology is a canary device, which warns of the impending risk of failure through loss of function before other important parts become severely impaired. In a BGA package, thermal fatigue of solder joints normally starts from the solder joints at the outermost part of the package. This can be taken advantage of by using the outermost solder joints as canary devices for detecting the degree of cumulative mechanical fatigue damage. To accurately estimate the lifetimes of other functional solder joints, it is essential to understand the relationship between the fatigue lives of canary joints and other functional joints. Damage path simulation is therefore proposed for predicting the crack propagation in solder joints on electronic packages through numerical simulation. During the process of designing the layout of canary joints and other joints, it is very useful to know not only the relationship between the fatigue lives of the canary and other joints, but also the path of crack propagation through all joints. This paper presents a method for estimating the relationship between the fatigue lives of canary joints and other joints by using damage path simulation. Some BGA packages mounted on a printed circuit board are modeled to demonstrate the process of estimating the lifetime of each joint under thermal cycle loading. A large-scale finite element model is used to accurately represent the geometrical properties of the printed circuit board and package. Both crack initiation and crack propagation processes can be simultaneously evaluated by modeling all of the solder joints on each package. The results show that damage path simulation and large-scale modeling are useful for determining the layout of canary joints in electronic packages.Copyright

Prognostic Health Monitoring Method for Fatigue Failure of Solder Joints on Printed Circuit Boards Based on a Canary Circuit

Continuing improvements in both capacity and miniaturization of electronic equipment such as solid state drives (SSDs) are spurring demand for high-density packaging of NAND-type flash memory mounted on SSD printed circuit boards. High-density packaging leads to increased fatigue failure risk of solder joints due to the decreased reliability margin for stress. We have developed a failure precursor detection technology based on fatigue failure probability estimation during use. This method estimates the cycles to fatigue failure of an actual circuit by detecting broken connections in a canary circuit (a dummy circuit of daisy-chained solder joints). The canary circuit is designed to fail earlier than the actual circuit under the same failure mode by using accelerated reliability testing and inelastic stress simulation. The statistical distribution of the strain range of solder joints can be provided by Monte Carlo simulations based on the finite element method and random load modeling. A feasibility study of the failure probability estimation method is conducted by applying the method to a printed circuit board on which a ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint’s fatigue failure.© 2013 ASME

Prognostic health monitoring method for printed circuit boards subjected to random cyclic loads

For random dynamic loads such as cyclic shock and vibration of semiconductor modules, a method using field load assessment and fatigue life estimation is proposed in order to improve the reliability of electronic products. The evolutionary spectrum method is introduced for random dynamic load modeling. The statistical distribution of structural responses such as the deformation and strain of solder joints and printed circuit boards can be predicted by Monte Carlo simulations based on the finite element method and random dynamic load modeling. A feasibility study of the failure probability estimation method is conducted for application to a printed circuit board on which a flip-chip ball grid array (BGA) package is mounted using BGA solder joints. The proposed method is found to be useful for prognostic health monitoring of solder joint failure.

Health monitoring method for load assessment in reliability design of printed circuit board

Health monitoring technologies, which can evaluate the performance degradation, load history and degree of fatigue, have the potential to improve the maintenance, the reliability design method and the availability in improper use conditions of electronic equipment. In this paper, we propose a method to assess the cooling performance degradation and load history of printed circuit boards by use of a hierarchical Bayes model based on CAE results of stress simulation and experiment data from actual measurements. We applied this method to note PC. It is confirmed that this method can estimate the structural response index distribution of the printed circuit board from monitoring variables, and that the statistical load assessment concerning cyclic load and the maximum load distribution can be conducted.

TESTING METHOD FOR MEASURING IMPACT STRENGTH OF BGA SOLDER JOINTS ON ELECTRONIC PACKAGE

A pendulum-impact testing machine was developed to measure the impact strength of ball-grid-array (BGA) solder joints between an electronic package and a circuit board. Ball solders were connected to daisy-chain between a dummy electronic package and a circuit board. The upper side of the package was directly bonded to a load cell. The rear side of the circuit board was also bonded to an aluminum alloy block fixed on a base. A pendulum made of aluminum alloy was collided into the load cell to apply tensile impact to the solder joints through the load cell. The history of the impact load could be controlled by raising the angle of the pendulum. The fracture of a BGA solder joint was detected by measuring the resistance of the daisy-chain circuit on the board. Therefore, the impact strengths of the solder joints at electrical disconnection and mechanical breaking of all joints could be determined. The experimental results showed that this method is useful for measuring the impact strength of BGA solder joints.