Katsumi Tsuneno

Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology

Effects of statistical process variation on the 0.25-/spl mu/m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSFs (response surface functions) for threshold voltage (V/sub th/) and saturation drain current (I/sub ds/). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V/sub th/ and 3% error in I/sub ds/. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS /spl Delta/I/sub ds/ in the production process. Furthermore we have designed an optimized 0.25-/spl mu/m CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V/sub th/ and I/sub ds/ variations of the 0.25-/spl mu/m CMOS exhibit less than 10% I/sub ds/ variation in the production level process, which is similar to the value of 0.35-/spl mu/m CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-/spl mu/m device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication.

A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification

This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.

Rigorous statistical process variation analysis for quarter-/spl mu/m CMOS with advanced TCAD metrology

Effects of statistical process variation on 0.35 /spl mu/m CMOS performance have been rigorously characterized using a new calibrated TCAD metrology. To achieve the variation analysis, a series of TCAD was conducted based on DoE with optimum variable transformations, which results in an RSF (Response Surface Function) for threshold voltage (Vth) and saturation drain current (Ids). A new global calibration of the RSF based on experimental data gives excellent accuracy of the RSF model within 0.02 V error in the Vth and 3% error in the Ids. Using the calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of gate-oxide formation process (oxide thickness: Tox) shows the most significant effect on the NMOS /spl delta/Ids in the production process. Furthermore, we have designed an optimized 0.25 /spl mu/m CMOS process and device based on the RSF, and also predicted its process variation effect on the device performances. It is clarified that the Vth and Ids variations of the 0.25 /spl mu/m CMOS show less than 10% for Ids in production level process, which is a similar value to the 0.35 /spl mu/m CMOS experimental data. Also additional TCAD for MOS model parameter generation, for the 0.25 /spl mu/m device, was conducted to allow circuit-designers to use predictive worst-case circuit design parameters before experimental chip fabrications.

TCAD strategy for predictive VLSI memory development

This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based predictive circuit model parameter generation for chip design purposes is one of the key topics in TCAD. A process and device database has been constructed, which is used in newly developed TCAD global calibrations in conjunction with a statistical process-recipe design at sub-half micron level. One month of TCAD was required to generate an optimized sub-half micron process and devices and channel-length dependent MOS model parameters. It was verified that the generated MOS circuit model agrees well with experiments within the predicted process fluctuation limit due to the proposed global TCAD calibration technique.<<ETX>>

A new hierarchical RSM for TCAD-based device design to predict CMOS development

A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM (Response Surface Method) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process/device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01 V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development.

A novel unified transient enhanced diffusion model on the basis of RSF with process database

A novel unified TED (transient enhanced diffusion) model for RTA and furnace processes is proposed on the basis of the vacancy-assisted diffusion model. The effective diffusivity is described by a RSF (response surface function) based on relaxation-time approximation of point defects, which depends on the annealing temperature and implant dose. The parameters were calibrated with a database set of experimental test structures. The ramp-up effect is taken into account with a new damage relaxation budget equation. In particular, the BF/sub 2/ implant-induced damage was demonstrated. It results in an excellent experimental agreement within /spl Delta/xj<0.01 /spl mu/m for xj=0.08-0.15 /spl mu/m N/P junction formations.

TCAD/DA for MPU and ASIC development

We have proposed, in this paper a, TCAD/DA methodology for MPU and ASIC with updated processes and devises, which allow a predictive chip-design with quick quantitative correlation studies between process-recipe and CKT and delay parameters required in DA works. Effects of statistical process variation on 0.35 /spl mu/m CMOS have been rigorously characterized with a new global TCAD calibration technique. Based on the data, process variation effects on a 0.25 /spl mu/m CMOS have been predicted, which is concluded that the Vth and Ids total-variation of the 0.25 /spl mu/m CMOS shows less than 10% in production process, which is similar with that of the 0.35 /spl mu/m CMOS.

A SPICE-compatible model of SG-MONOS for 28nm flash macro design considering the parasitic resistance caused by trapped charges

A SPICE-compatible model for the read current of split-gate MONOS (SG-MONOS) cell has been developed for 28nm embedded flash macro design. The influence of trapped charges on the read current has been analyzed by using TCAD. It has been found that trapped charges located on top of the gap region strongly decrease the cell current. It has been also found that the shape of Id-Vsg curve changes drastically depending on the positon of trapped charge and trap density. This paper proposes a new model which reproduces the above behavior by using a synthesis of several resistances in which every resistance changes its value exponentially to the gate voltage. The model shows an excellent fitting accuracy for 28nm generation cell.

TCAD diagnosis of I/O-pin latchup in scaled-DRAM

Summary form only given. This paper describes a TCAD analysis of I/O-pin latchup failure found in a shallow-well CMOS DRAM. The 0.35 /spl mu/m DRAM I/O-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified the biasing effect of the guard-band (N/sup +/) layer and the layout-related latchup mechanism, which leads to a practical latchup-immunity design in sub-/spl mu/m CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35 /spl mu/m DRAM.

A novel transient enhanced diffusion model of phosphorus during shallow junction formation

High-dose ion implantation and low temperature annealing are one of the key technologies for shallow junction fabrication in quarter-micron CMOS VLSIs. It is well known that transient enhanced diffusion (TED) of implanted dopants dominates in diffusion mechanism at low temperature furnace annealing and RTA (Rapid Thermal Annealing). We reported an empirical compact model of TED which describes its dependency on implant doses and annealing temperature. However, the model assumes effective diffusivity during the 10 minutes in furnace annealing, therefore it fails to describe time-dependent TED effect such as short-time RTA and ramping-effect in furnace annealing. In this work, a new study on transient enhanced diffusion is discussed, which is focused on the RTA process for phosphorus diffusion. The dependency of annealing time on TED phenomenon is newly characterized as parameters of annealing temperature and implant dose in the new model.