Hisako Sato

A new defect distribution metrology with a consistent discrete exponential formula and its applications

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data.

Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology

Effects of statistical process variation on the 0.25-/spl mu/m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSFs (response surface functions) for threshold voltage (V/sub th/) and saturation drain current (I/sub ds/). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V/sub th/ and 3% error in I/sub ds/. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS /spl Delta/I/sub ds/ in the production process. Furthermore we have designed an optimized 0.25-/spl mu/m CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V/sub th/ and I/sub ds/ variations of the 0.25-/spl mu/m CMOS exhibit less than 10% I/sub ds/ variation in the production level process, which is similar to the value of 0.35-/spl mu/m CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-/spl mu/m device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication.

A new characterization of sub-/spl mu/m parallel multilevel interconnects and its experimental verification

This paper describes a new interconnect design and its verification with test-structures for sub-micron multilevel interconnection. A universal design-chart has been developed, which gives a precise sub-micron interconnect-capacitance for parallel multilevel interconnections. Test-structure measurements show excellent agreement with the design-chart within 4% error. A simple propagation delay model has also been developed.

Rigorous statistical process variation analysis for quarter-/spl mu/m CMOS with advanced TCAD metrology

Effects of statistical process variation on 0.35 /spl mu/m CMOS performance have been rigorously characterized using a new calibrated TCAD metrology. To achieve the variation analysis, a series of TCAD was conducted based on DoE with optimum variable transformations, which results in an RSF (Response Surface Function) for threshold voltage (Vth) and saturation drain current (Ids). A new global calibration of the RSF based on experimental data gives excellent accuracy of the RSF model within 0.02 V error in the Vth and 3% error in the Ids. Using the calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of gate-oxide formation process (oxide thickness: Tox) shows the most significant effect on the NMOS /spl delta/Ids in the production process. Furthermore, we have designed an optimized 0.25 /spl mu/m CMOS process and device based on the RSF, and also predicted its process variation effect on the device performances. It is clarified that the Vth and Ids variations of the 0.25 /spl mu/m CMOS show less than 10% for Ids in production level process, which is a similar value to the 0.35 /spl mu/m CMOS experimental data. Also additional TCAD for MOS model parameter generation, for the 0.25 /spl mu/m device, was conducted to allow circuit-designers to use predictive worst-case circuit design parameters before experimental chip fabrications.

TCAD strategy for predictive VLSI memory development

This paper describes a methodology of TCAD application in VLSI design and development. Simulation-based predictive circuit model parameter generation for chip design purposes is one of the key topics in TCAD. A process and device database has been constructed, which is used in newly developed TCAD global calibrations in conjunction with a statistical process-recipe design at sub-half micron level. One month of TCAD was required to generate an optimized sub-half micron process and devices and channel-length dependent MOS model parameters. It was verified that the generated MOS circuit model agrees well with experiments within the predicted process fluctuation limit due to the proposed global TCAD calibration technique.<<ETX>>

Inactivation of Low‐Dose Implanted Phosphorus Pileup in the Silicon Side of an Si / SiO2 Interface after Oxidation

Precise phosphorus profiles were obtained in the region of an Si/SiO 2 interface by means of inductively coupled plasma mass spectrometry (ICPMS), secondary ion mass spectroscopy (SIMS), and spreading resistance profiling (SRP) measurements. Samples were prepared by implanting phosphorous at low dose, annealing, and oxidizing by wet oxidation. According to ICP-MS, the total amounts of phosphorus were extremely low in the SiO 2 side. The same results held when the oxidation temperature was changed from 800 to 900°C. SIMS measurement in conjunction with ICP mass measurement showed that the pileup of phosphorus occurred in the silicon side at the Si/SiO 2 interface. SRP confirmed that the pileup of phosphorus was electrically inactive. As a result, the active amount of phosphorus in the Si side was reduced to about 60%. The simulation based on the monolayer formation at the the SiO 2 /Si interface was proposed to describe the observed pileup phenomenon of phosphorus.

Discrimination of clustered defects on wafers using statistical methods

This paper presents a method for discrimination of clustered defects. The histogram of the number of defects per die is approximated to several major distributions. As a result, we found that Poisson distribution is almost equivalent to real data. The advantage of this method is that accurate coordinates are not required. Therefore it can be applied for almost all tools regardless of their accuracy of coordinates.

A new hierarchical RSM for TCAD-based device design to predict CMOS development

A new methodology in simulation-based CMOS process designs has been proposed, using a hierarchical RSM (Response Surface Method) and efficient experimental calibrations. The new design methodology has been verified in a half-micron CMOS process/device development using the test structure, which results in reliable prediction of the threshold voltage (Vth) and drain current (Ids) within 0.01 V and 0.84% errors, respectively. This method has also reduced simulation works to about one half required by the conventional RSM. TCAD based RSM is applied for predicting quarter-micron CMOS development.

Evaluation Of Two-dimensional Transient Enhanced Diffusion Of Phosphorus During Shallow Junction Formation

shallow junctions fabrication in quarter-micron CMOS VLSIs. It is well known that transient enhanced diffusion (TED) of implanted dopants dominates in diffusion mechanism at low temperature furnace annealing. [ 11-[5] However, dependence of transient diffusivity increase on implant doses remains unclear. In this work, a new study on transient enhanced diffusion are described focused on phosphorus implant and furnace annealing process. We found the anomalous diffusion is implanted-dose dependent as well as annealing temperature dependent.[4] Critical doses for Phosphorous enhanced diffusion has been determined in 950C annealing condition, which might be a function of annealing temperature. Two-dimensional effect of the phenomena has been also verified, showing that the TED in phosphorous is close to isotropic. 2. Experiments and Simulation We evaluated about forty samples of phosphorus doping-profile fabricated with various process conditions. Dopant depth-profiles are measured by SIMS analysis with CAMECA-ims4f. Lateral diffusion profile obtained by CV method [7] is refereed to verify 2D diffusion in Phosphorous shallow junction. Analytical distribution model (Dual-Pearson4) and Monte Carlo simulation are used to analyze ion-implant profiles. In dopant-diffusion simulation, vacancy-assisted diffusion model is adopted in which the TED diffusivity parameters were calibrated.[6] In order to compare between simulation and experiment, we introduced an RMS error defined in [6]. 3. Results and Discussion As-implanted phosphorus profiles obtained from si yulation and SIMS measurement are shown in Figure 1, for the implantation conditions of 1 x10i4/cm dose and 5OKeV acceleration-energy. As shown in the figure, both profiles coincide each other within an error of 0.8%. To demonstrate transient enhanced diffusion during Phosphorous fumace annealing, simulation without TED effect is conducted and compared with experiment as shown in Figure. 2, showing a large discrepancy at the tail parts of profile after lOmin fumace annealing at 950C. TED parameter (transient effective diffusivity) is determined in such a way that the both profiles get a good fit within RMS error of less than 2%, as shown in Figure. 3. Dose dependency of the TED parameter is shown in Figure 4 for 50 minutes 950C annealing. As shown in the fi ure, the parameter shows a constant value of D/Do=l6, when the total dose is higher than lx104/cm . On the other hand, no transient enhanced diffusion is observed when the implant dose is lower than lx10i3/cm2. It is also proved that the TED parameter in Phosphorous diffusion is approximately independent of implant-energy and annealing time as shown in Figure 3 and 4, as an example. In Figure 5, we summarized the dependency of extracted enhanced diffusivity (normalized) on implant doses at 820-920C anneakg. Jt is shown that diffusivity increases with dose between the dose of 1x10 /cm and 1x10 /cm at 950C, but it saturates at higher dose than 1x10i4/cm2. It is seen that the transient region of TED effect might be temperature dependent to a certain extent. Two-dimensional Phosphorus shallow junction formation under 2x1 O13/cm2 dose is investigated by Monte Carlo and diffusion simulations with TED parameter. It is shown in Figure 6. Lateral profile (at surface) and vertical (depth) profile are verified by comparing simulation and experimental results as shown in Figure 7. In the simulation, the TED parameter is assumed to be isotropic. Using the isotropic TED parameter, phosphors profiles along the silicon surface agrees well with experimental profile within an error of 0.5%. 4. Acknowledgement

An efficient method of applying hot-carrier reliability simulation to logic design

This paper presents an efficient application of hot carrier reliability simulation to 0.18 /spl mu/m and 0.14 /spl mu/m gate length logic products. Using analysis of simple primitive inverter cells, a design rule was developed in restricting signal rise time, and delay libraries of actual products which were screened to check whether the rise time restrictions were met. At 200 MHz, maximum rise time (0-100%) triseMAX was 0.8 ns (17% of duty) under /spl Delta/td/td=5%. For a 800,000 net product, only 25 simulations were done (each less than one minute CPU time) for the internal devices with screening done for this logic process. 30 nets were caught, but judged reliable due to their reduced duty.