Katsunori Asano

High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112~0) face: 17 times higher (95.9 cm/sup 2//Vs) than that on the conventional (0001) Si-face (5.59 cm/sup 2//Vs). A low threshold voltage of MOSFETs on the (112~0) face indicates that the (112~0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (/spl mu//sub (11~00)///spl mu//sub (0001)/=0.85) reflects the small anisotropy in bulk electron mobility.

12-19 kV 4H-SiC pin diodes with low power loss

12-19 kV 4H-SiC UHV pin diodes have been developed for the first time. The developed UHV diodes have a low V/sub F/ of less than 1/4/sup th/ and short trr of less than 1/30/sup th/, as compared with those of commercialized 6 kV Si diodes. Therefore, they can drastically reduce both the conduction loss and the switching loss of electric power conversion equipment.

Development of Ultrahigh-Voltage SiC Devices

Ultrahigh-voltage silicon carbide (SiC) devices [p-i-n diodes and insulated-gate bipolar transistors (IGBTs)] and switching test have been investigated. As a result, we have succeeded in developing a 13-kV p-i-n diode, 15-kV p-channel IGBT, and 16-kV flip-type n-channel implantation and epitaxial IGBT with a low differential specific on-resistance (Rdiff,on). It was revealed that a power module fabricated using a nanotech resin, Si3N4 ceramic substrate, and W base plate was suitable for ultrahigh voltage and high temperature. A switching test was carried out using a clamped inductive load circuit, which indicated that the energy loss of a circuit with ultrahigh-voltage SiC devices is lower than that of Si devices.

Investigation of Basal Plane Dislocations in the 4H-SiC Epilayers Grown on {0001} Substrates

In this paper, we investigated the density of basal plane dislocations (BPDs) in 4H-SiC epilayers grown on (0001) and (000-1). Re-polishing of the substrate surface, in-situ H2 etching and off-cut angle were found to influence the propagation of BPDs into the epilayers. The epitaxial growth on (000-1) substrates yields a relatively low density of BPDs compared to growth on (0001). The electrical characteristics of pn diodes were also investigated, and the suppressed forward degradation and high-voltage blocking performance were obtained in the use of the (000-1) epilayers.

Enhancement and control of carrier lifetimes in p-type 4H-SiC epilayers

Enhancement and control of carrier lifetimes in p-type 4H-SiC have been investigated. In this study, thermal oxidation and carbon ion implantation methods, both of which are effective for lifetime enhancement in n-type SiC, were attempted on 147-μm thick p-type 4H-SiC epilayers. Effects of surface passivation on carrier lifetimes were also investigated. The carrier lifetimes in p-type SiC could be enhanced from 0.9 μs (as-grown) to 2.6 μs by either thermal oxidation or carbon implantation and subsequent Ar annealing, although the improvement effect for the p-type epilayers was smaller than that for the n-type epilayers. After the lifetime enhancement, electron irradiation was performed to control the carrier lifetime. The distribution of carrier lifetimes in each irradiated region was rather uniform, along with successful lifetime control in the p-type epilayer in the range from 0.1 to 1.6 μs.

4H-SiC high power SIJFET module

5kV high power full SiC module technology was developed and 1.6kV 40A SIJFET module was fabricated for the first time, which is the pressure contact flat package type and includes four 6mm /spl times/ 6mm SiC SIJFETs in addition to one 6mm /spl times/ 6mm SiC fly wheeling pn diode. SiC SIJFET operates as the bipolar transistor and its current gain ranges from 20 to 4000. Its turn-on time and turn-off time are 360ns and 109 ns respectively. Since the SIJFET module has not only high current gains but also high switching speeds, it is suitable for the low loss power conversion circuits.

5.5 kV normally-off low RonS 4H-SiC SEJFET

A normally-off type 5.5 kV 4H-SiC JFET with low specific on-resistance, called SEJFET (Static Expansion channel JFET), has been fabricated. Its normally-off operation was realized by a thin regrown epitaxial channel layer and using the buried p/sup +/ regions as a gate in addition to the top p/sup +/ regions. The achieved blocking voltage (BV) is the highest BV among the reported SiC switching devices. By the expansion of the channel region under the positive biases of both gates, specific on-resistance (R/sub on/S) can be reduced and 218 m/spl Omega/cm/sup 2/ achieved. Furthermore, a 4H-SiC SEJFET with a BV of 4.45 kV has been fabricated, which has the largest figure of merit BV/sup 2//RonS of 164 MW/cm/sup 2/.

Characteristics of a 4H-SiC Pin Diode With Carbon Implantation/Thermal Oxidation

The forward voltage drops of pin diodes with the carbon implantation or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of pin diodes with the standard or carbon implantation process show almost the same tendency. In the reverse recovery characteristics at 250 °C, pin diodes with the carbon implantation process, however, have the longer reverse recovery time than those with the standard process. These characteristics suggest that the forward voltage drops depend on the bulk carrier lifetime. In the reverse recovery characteristics, other recombination paths, such as interface or surface recombination, become dominant.

1.4 kV 4H-SiC UMOSFET with low specific on-resistance

A device concept for an SiC MOSFET of 5 kV/spl middot/3 kA class is proposed. As the first step in developing the device, a 2 kV SiC UMOSFET with a punch-through structure has been designed and fabricated. The fabricated UMOSFET has a high breakdown voltage of 1.4 kV and a low specific on-resistance of 311 m/spl Omega//sup ./cm/sup 2/ at room temperature, and surpasses Sis theoretical limit of relationships between breakdown voltage and specific on-resistance.

Impacts of reduction of deep levels and surface passivation on carrier lifetimes in p-type 4H-SiC epilayers

Impacts of reduction of deep levels and surface passivation on carrier lifetimes in p-type 4H-SiC epilayers are investigated. The authors reported that the carrier lifetime in n-type epilayers increased by reduction of deep levels through thermal oxidation and thermal annealing. However, the carrier lifetimes in p-type epilayers were not significantly enhanced. In this study, in order to investigate the influence of surface passivation on the carrier lifetimes, the epilayer surface was passivated by different oxidation techniques. While the improvement of the carrier lifetime in n-type epilayers was small, the carrier lifetime in p-type epilayers were remarkably improved by appropriate surface passivation. For instance, the carrier lifetime was improved from 1.4 μs to 2.6 μs by passivation with deposited SiO2 annealed in NO. From these results, it was revealed that surface recombination is a limiting factor of carrier lifetimes in p-type 4H-SiC epilayers.