Tetsuya Miyazawa

Enhanced annealing of the Z1∕2 defect in 4H–SiC epilayers

The authors investigated the application of the carbon-implantation/annealing method for the annealing of the main lifetime limiting defect Z1∕2 in thick 4H–SiC epilayers. Examination of different implantation doses and annealing temperatures showed that finding the optimum conditions is crucial for obtaining thick layers with carrier trap concentration below 1011cm−3 in the whole 100μm epilayer. The carrier lifetime increased from less than 200ns to over 1μs at room temperature in the samples annealed with the carbon-implanted layer. The thick 4H–SiC epilayers after the application of the carbon-implantation/annealing were confirmed to be applicable for fabrication of high-voltage bipolar devices and resulted in improved conductivity modulation. Possible annealing mechanisms are discussed in detail making a comparison between annealing of as-grown material and irradiated material.

Evaluation of long carrier lifetimes in thick 4H silicon carbide epitaxial layers

The carrier lifetime of ∼265 μm thick n-type 4H silicon carbide epilayers prepared using the carbon-implantation/annealing method was evaluated. An extraordinarily long minority carrier lifetime of 18.5 μs and a high injection lifetime of 19.2 μs were evaluated from time-resolved photoluminescence and microwave photoconductivity decay measurements, respectively. Based on the relationship between the epilayer thickness and carrier lifetime, the influence of surface recombination on the carrier lifetime was eliminated, and the bulk lifetime and hole diffusion constant were discussed.

Characteristics of a 4H-SiC Pin Diode With Carbon Implantation/Thermal Oxidation

The forward voltage drops of pin diodes with the carbon implantation or thermal oxidation process using a drift layer of 120 μm thick are around 4.0 V and are lower than those with the standard process. The reverse recovery characteristics of pin diodes with the standard or carbon implantation process show almost the same tendency. In the reverse recovery characteristics at 250 °C, pin diodes with the carbon implantation process, however, have the longer reverse recovery time than those with the standard process. These characteristics suggest that the forward voltage drops depend on the bulk carrier lifetime. In the reverse recovery characteristics, other recombination paths, such as interface or surface recombination, become dominant.

Point defect reduction and carrier lifetime improvement of Si- and C-face 4H-SiC epilayers

The impact of two post-growth processes, namely, C+-implantation/annealing process and thermal oxidation/annealing process, on trap concentrations in thick n-type 4H-SiC epilayers was studied for both Si- and C-face. Conditions such as the implantation dose and annealing temperature of the C+-implantation/annealing processes were optimized for Si-face epilayers, and consequently the Z1/2 center was eliminated up to 100 μm or more, and the minority carrier lifetime reached 13 μs while maintaining a good surface morphology. The effect of the process conditions on the creation of new traps, including ON1 center, was also studied in both Si- and C-face epilayers. The ON1 center was introduced in both Si- and C-face by two post-growth processes, although the concentration was found to vary according to the polar face and the post-growth processes. The mechanism of the different impacts on Z1/2 center reduction and ON1 center creation by the two post-growth processes on Si- and C-face is discussed.

Short minority carrier lifetimes in highly nitrogen-doped 4H-SiC epilayers for suppression of the stacking fault formation in PiN diodes

We investigated the dependency of minority carrier lifetimes on the nitrogen concentration, temperature, and the injected carrier concentration for highly nitrogen-doped 4H-SiC epilayers. The minority carrier lifetimes greatly shortened when the nitrogen concentration exceeded 1018 cm−3 through enhancing direct band-to-band and Auger recombination and showed a slight variation in the temperature range from room temperature (RT) to 250 °C. The epilayer with a nitrogen concentration of 9.3 × 1018 cm−3 exhibited a very short minority carrier lifetime of 38 ns at RT and 43 ns at 250 °C. The short minority carrier lifetimes of the highly nitrogen-doped epilayer were confirmed to maintain the values even after the subsequent annealing of 1700 °C. 4H-SiC PiN diodes were fabricated by depositing a highly nitrogen-doped epilayer as a “recombination enhancing layer” between an n− drift layer free from basal plane dislocations and the substrate. The PiN diodes showed no formation of stacking faults and no increase i...

Enhancement of carrier lifetime in lightly Al-doped p-type 4H-SiC epitaxial layers by combination of thermal oxidation and hydrogen annealing

We investigated the enhancement of carrier lifetime in lightly Al-doped p-type 4H-SiC epilayers (NA ≃ 2 × 1014 cm−3) by postgrowth processing. A carrier lifetime of 2.8 µs in an as-grown epilayer is increased to 5.1 µs by carbon vacancy elimination, i.e., thermal oxidation at 1400 °C for 48 h. It reaches 10 µs by subsequent hydrogen annealing at 1000 °C for 10 min. The carrier lifetime in the as-grown epilayer is also increased to 4.0 µs by only hydrogen annealing. These results suggest that, in addition to carbon vacancy, there is another lifetime killer in p-type SiC, which cannot be eliminated by thermal oxidation but can be passivated by hydrogen annealing.

Low-Pressure Fast Growth and Characterization of 4H-SiC Epilayers

Fast and thick 4H-SiC epitaxial growth is demonstrated in a vertical-type reactor under a low system pressure within the range 13-40 mbar. A very fast growth rate of up to 250 m/h is obtained. The material quality of the epilayers grown in the reactor is evaluated by low-temperature photoluminescence, deep level transient spectroscopy, microwave photoconductive decay, synchrotron topography and room temperature PL imaging. The carrier lifetime of thick epilayers with or without the application of the C+-implantation/annealing method and extended defects in the epilayers grown on 8º and 4º off substrates are discussed.

Critical Conditions of Misfit Dislocation Formation in 4H-SiC Epilayers

Thermal annealing experiments were performed to determine the critical conditions of misfit dislocation formation in 4H-SiC epilayers in a temperature range of 1400-1800 °C. Misfit dislocations were observed to form at a given annealing temperature if the temperature gradient across the epi-wafer exceeded a critical value. It was also found that two types of interfacial dislocations could form under different stress conditions. Their formation mechanisms are discussed.

Epitaxial Growth of Thick Multi-Layer 4H-SiC for the Fabrication of Very High-Voltage C-Face n-Channel IGBT

The epitaxial growth of thick multi-layer 4H-SiC to fabricate very high-voltage C-face n-channel IGBTs is demonstrated using 3-inch diameter wafers. We employ an inverted-growth process, which enables the on-state voltage of resultant IGBTs to be reduced. Furthermore a long minority carrier lifetime (> 10 μs) and a low-resistance p+ epilayer can reduce the forward voltage drop of the IGBTs. The small forward voltage drop is demonstrated particularly at high temperatures by fabricating and characterizing simple pin diodes using the epi-wafer.

Component Technologies for Ultra-High-Voltage 4H-SiC pin Diode

Forward voltage drops of carbon implanted and thermal oxidized pin diode with thick drift layer are investigated to evaluate the effect on the lifetime. The forward voltage drops of the carbon implanted and thermal oxidized pin diodes with drift layer of 120 μm thick were around 4.0 V. Furthermore, blocking characteristics of 4H-SiC pin diodes with mesa-JTE, which were fabricated on C-face and Si-face substrates, are also investigated. The breakdown voltages of pin diodes with 250 μm and 100 μm epitaxial layers are 17.1 kV and 10.9 kV, respectively.