Sharad Prasad

The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation.

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I/sub g/ versus V/sub g/ characteristics for the p/sup +//pMOSFET are essentially identical to those for the n/sup +//nMOSFET; however, when measured in inversion, the p/sup +//pMOSFET exhibits much lower gate current for the same |V/sub g/|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p/sup +//pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p/sup +/-polysilicon gate; and (3) conduction band electron tunneling from the p/sup +/-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p/sup +//pMOSFET, with one of them dominating in a certain voltage range.

Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

Electron beam probing is a powerful technique for analyzing functional failures in integrated circuits. A common approach used for isolating defects is to trace a bad signal on a failing pin through the circuit. The inputs and outputs of each logical node can be compared against simulated results to determine functionality. This method has several limitations which are discussed in this paper -- most notably, it is often an extremely time consuming process. Scan- path designs have been introduced which increase the observability and controllability of internal circuit nodes. The use of ASIC scan-path architecture is increasing due to the improved testability compared to non-scan designs. Scan-path architecture also offers opportunities for more efficient failure analysis of functional failures. In this paper we present a successful method of defect isolation using scan-path testing in conjunction with electron beam probing. Using this method, a fault area or node is identified using a test datalog, and the defect is precisely located using an electron beam probe station. This paper discusses in detail the integration of scan testing with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements.

Key hot-carrier degradation model calibration and verification issues for accurate AC circuit-level reliability simulation

This study provides necessary degradation model calibration and evaluation guidelines required to enable more consistent and effective use of hot-carrier reliability simulation tools. Benchmark results provide strong verification that the AC degradation models are generally accurate if properly calibrated; however, SPICE modeling errors, secondary physical mechanisms and statistical parameter variation are found to impact the simulated results as much as differences in the circuit design itself.

Assessing and characterizing inter-and intra-die variation using a statistical metrology framework: A CMP case study

As device dimensions continue to shrink below half micron dimensions and the demand for both yield and performance rises, the assessment and control of process and device variation becomes critical. Yield loss from parametric sources will rise unless process margins are characterized to a higher degree than currently available [1]. Process and device variation in VLSI manufacturing occurs with different scope and extent. Process perturbation, drifts, and equipment factors result in lot-to-lot variation, while within-wafer variation may stem from process non-uniformities. While substantial work has focused on the control of lot and wafer-level variation [2], die-level variation has received little attention despite the potential impact on circuit performance [3]. This spatial variation has both systematic and random components. Currently, device variation is often lumped into a single large distribution as part of a “worstcase” approach to modeling. A methodology is needed to transform this large distribution into deterministic components that can be compensated or designed around. We present statistical metrology as a methodology to assess variation and parameterize any resulting circuit and process impact. Variation assessment is achieved by identifying and explicitly modeling the individual sources of variation. The resulting quantification of variation components enables better process modeling, facilitates process control, and provides realistic data for statistical circuit modeling. In this paper we use statistical metrology methods to study inter-level dielectric (ILD) thickness variation for two representative chemical-mechanical polishing (CMP) processes. We suggest that three phases of experimental design are appropriate to (1) identify important factors; (2) construct explicit variation models, and (3) quantify the impact of variation in realistic chip environments. We present a case study in which these phases as well as new modeling methods, in particular a modified form of repeated measure ANOVA (Analysis of Variance), are used to model dieand waferlevel variation for representative CMP/ILD processes. STATISTICAL METROLOGY METHODOLOGY

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.

Statistical metrology for characterizing CMP processes

Abstract CMP processes are used to planarize layers; however, variations in ILD thickness due to various layout factors can affect the modelling of interconnect parameters. In this paper an overview of ‘Statistical Metrology’ for CMP processes is presented. Using statistical metrology for CMP the process or interconnect design rules can be optimized for minimal variations.

Slight gate oxide thickness increase in PMOS devices with BF 2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF/sub 2/ implanted p/sup +/ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 /spl Aring/ regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon.

Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs are presented and additional new test circuit designs demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed.

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.