Uday Panwar

Diode Switch: A Novel Technique for Mitigation of Leakage Power in DSM Technologies

As technology scales down below 65nm there is a rapid growth in semiconductor industries; reduction in transistor size leads to exponential increase in power consumption in DSM technology. The major concerns of VLSI designers are to develop a circuit which is having high performance with minimal size earlier. The fast growth in portable computing and wireless communication has led to the power dissipation along with heating. In this paper we have implemented a novel leakage reduction technique known as Diode switch (Combination of PMOS and NMOS sleep transistor) and inserted a sleep transistor above PUN and below PDN which increases the resistance of the circuit. By inserting the sleep transistor short circuit power consumption reduces which rail the circuit from supply voltage, but there is penalty of area take place. All the simulation is performed 32nm technology by using HSPICE simulator. Proposed DHS circuit reduce 48.98%, DFS reduces 52.89% and DHFS reduces upto 68.27% of leakage power.

Gate replacement technique with thick T ox to mitigate leakage with zero delay penalty for DSM CMOS circuit

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Here a wide-ranging survey and analysis has been done for leakage reduction based on active as well as idle mode of operation. This paper proposes a novel approach, based on run time leakage reduction, where a logic gate having Worst Leakage State (WLS) is replaced by some variation of standard logic cell having minimum leakage with the same input vector. For this purpose oxide thickness (Tox) of standard logic cell is increased to 2nm which highly reduces the leakage current and simultaneously increase in the W/L ratio of transistor for zero delay penalties due to gate replacement of the circuit is done. Proposed approach is based on gate replacement technique for reducing leakage without technology modification of IC. The Proposed approach achieves 88.39% average reduction in leakage current as compared with the conventional circuit leakage current with zero delay penalties, while basic gate replacement technique gives only 69.3%.

Leakage Reduction by Integrating IVC and ALS Technique in 65 nm CMOS One Bit Adder Circuit

In Deep Sub-Micron (DSM) technology, leakage power is becoming the primary consideration, as it decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. Major design constraints are always area, power and delay in Very Large Scale of Integration (VLSI) circuits. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation. This paper proposes an integrated approach, based on Input Vector Control (IVC) with Auxiliary Logic Switch (ALS) applied on the circuit. Here ALS is the variant of conventional logic gate, which replaces the gates are in their Worst Leakage State (WLS). Firstly IVC is applied on the given circuit for finding the Minimum Leakage Vector (MLV) secondly ALS is applied for the particular MLV and achieves 52.6 % reduction in leakage power on a contrary of 18 % leakage reduction if only IVC is applied. Proposed technique is simulated for static CMOS circuit (i.e. 1 bit Adder) using HSPICE simulator with 65 nm technology file provided by BPTM. Circuit parameters such as dynamic power, leakage power, delay and area form the basis for the evaluation. The result of the analysis clearly shows a tradeoff between leakage power and other circuit performances parameters. Hence a designer or a Computer Aided Design (CAD) tool would be able to select the suitable leakage minimization technique as per their requirement.

An algorithmic approach for leakage current reduction in deep sub-micron CMOS circuits

There are several techniques available to control the leakage current in deep sub-micron technologies. One of the techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be minimized in the off state. In this paper, an algorithm has been given to calculate the best input vector that can be applied to the circuit (designed with 65nm technology transistors) in the off state for obtaining the low leakage current. The concept of controllability of the nodes in the circuit and the inter dependency of the gates in the circuit were used to determine the best input vector in the algorithm. Exclusive OR gate with NAND gates is used to test the algorithm, the results showed that the algorithm gives an input vector that can be applied to the circuit in the sleep state which is same as that of the vector obtained using an exhaustive search in CADENCE SPECTRE, with less computational time.

An Algorithm for Leakage Power Reduction through IVC in CMOS VLSI Digital Circuits

current in CMOS circuits can be controlled at the circuit level and at the device level as well. One of the circuit level control techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be reduced in the sleep state. In this paper, an algorithm has been given to determine the optimum input vector that can be applied to the circuit in the sleep state for getting low leakage power. This algorithm uses the concept of controllability of the nodes in the circuit and the dependency of a gate on the remaining gates in the circuit to determine the optimum input vector. The proposed algorithm has been applied on an ISCAS benchmark circuit C17, the results showed that the algorithm gives a vector having a leakage nearer to the vector obtained using exhaustive search in CADENCE that gives low leakage value with less execution time as well. Keywordscurrent control, Low leakage vector, VLSI digital circuits, Low leakage power, CMOS combinational circuits.

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. VLSI design constraints are always area, power and delay. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation Leakage power in CMOS VLSI circuits can be controlled at the circuit level. This paper has considered two run time leakage reduction mechanics i.e. Input Vector Control (IVC) and Gate Replacement (GR). When the first technique is applied on the CMOS circuit, 30% average leakage power reduction is achieved where as 46% of average leakage power is reduces due to GR technique. The Maximum leakage reduction is achieved of 41.2% and 73% due to IVC and GR techniques respectively. These techniques have been applied on ISCAS benchmark circuit C17 using TSMC0.18um technology file on HSPICE simulator.