Pawel Russek

AES hardware implementation in FPGA for algorithm acceleration purpose

In this paper we investigate hardware implementation of AES-128 cipher standard on FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve that problems custom architecture in reconfigurable hardware was proposed to speed up the performance and flexibility of Rijndael algorithm implementation. We aimed to achieve the maximum speed and efficiency of cipher process, therefore pipeline architecture of AES module was proposed. The investigations involved simulations and synthesis of VHDL code utilizing Virtex4 series of Xilinx.

Dedicated architecture for double precision matrix multiplication in supercomputing environment

The utilization of FPGA in supercomputing is an emerging idea. That is obviously due to the progress in semiconductor technology. Todays FPGA capacity allow for double precision floating point arithmetic implementation. In this paper authors present their approach to the custom matrix multiplication implementation. Matrix multiplication is a key operation in linear algebra scientific calculations. Presented architecture is dedicated to act as a part of reconfigurable accelerator for SGI Altix 4700 supercomputer system. Architecture of the hardware and synthesis results are presented.

Embedded zero wavelet coefficient coding method for FPGA implementation of video codec in real-time systems

The issues of video coding based on exceptionally suitable for SHD format Shapiro (1993) EZW (embedded zero wavelet) algorithm is discussed. The main aspect is a possibility of building a real time system which is able to process the algorithm. Thus a dedicated architecture for the purpose is considered. The method presented is based on the EZW method modified such a way to simplify the hardware architecture dedicated for its execution. Such a simplification allows one to use FPGA technology as a target platform for the system. The MISD (multiple instruction-stream single data-stream) architecture is proposed as a solution of the problem. The architecture is characterised by high speed execution of the EZW algorithm. Simplicity and performance classify the algorithm for implementation in high capacity programmable FPGA structures. The paper is the authors contribution in the worlds development of custom computing machines (CCM).

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration

Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback is the lack of a tool which could do it. HPC applications usually consist of a huge amount of a complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLLs (High Level Languages) such as Mitrion-C (Mohl, 2006). HLLs were invented to make the development of HPRC applications faster. Loop profiling is one of the steps to check if the insertion of an HLL to an existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with minimal initialization of it during the execution of algorithms.

Hardware implementation of the orbital function for quantum chemistry calculations

This paper presents FPGA acceleration and implementation results of a hardware module for generating orbital function. The authors have implemented some of the computationally demanding part of the GPP quantum chemistry source code in FPGA. The orbital function core is composed of the authors’ customized floating-point hardware modules. These modules are scalable from single to double precision, capable of working at frequency ranging from 100 to 200 MHz. Besides hardware implementation, the design process also involved reformulation of the algorithm in order to adapt them to the platform profile. The computational procedure presented in this paper is part of an algorithm for generating exchange-correlation potential, and is also recognized as one of the most computationally intensive routines. This feature justifies the effort devoted to develop its hardware implementation.

ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test

In this paper, we present the Arbitrary Precision Arithmetic Library - ArPALib, suitable for algorithms that require integer data representation with an arbitrary bit-width (up to 4096-bit in this study). The unique feature of the library is suitability to be synthesized by HLS (High Level Synthesis) tools, while maintaining full compatibility with C99 standard. To validate the applicability of ArPALib for the FPGA-enhanced SoCs, the Miller-Rabin primality test algorithm is considered as a case study. Also, we provide the performance analysis of our library in the software and hardware applications. The presented results show the speedup of 1.5 of the hardware co-processor over its software counterpart when ApPALib is used.

Study of the Parallel Techniques for Dimensionality Reduction and Its Impact on Performance of the Text Processing Algorithms

The presented algorithms employ the Vector Space Model (VSM) and its enhancements such as TFIDF (Term Frequency Inverse Document Frequency). Vector space model suffers from curse of dimensionality. Therefore various dimensionality reduction algorithms are utilized. This paper deals with two of the most common ones i.e. Latent Semantic Indexing (LSI) and Random Projection (RP). It turns out that the size of a document corpus has a substantial impact on the processing time. Thus the authors introduce GPU based on acceleration of these techniques. A dedicated test set-up was created and a series of experiments were conducted which revealed important properties of the algorithms and their accuracy. They show that the random projection outperforms LSI in terms of computing speed at the expanse of results quality.

Energy Efficient Calculations of Text Similarity Measure on FPGA-Accelerated Computing Platforms

This paper presents an impact of the customized hardware accelerator on the overall performance of the text similarity computing system. The hardware processing module that is presented in the paper is a building block of the processing engine in the search system of related documents. The engine is used in the phase of preliminary retrieval of similar documents. The TF-IDF weighting scheme and cosine similarity metric are used by the module. Evaluation boards equipped with Xilinx’s Field Programmable Gate Array (FPGA) were utilized as a hardware platforms for implementation of the selected time-consuming operations. The series of tests was conducted, and the results of the hardware-accelerated solutions were compared against the standard software implementation. The two different FPGA-enabled platforms were employed in the experiments. The low-power and the high-performance platform were used to compare the metrics of different hardware solutions. We provide the adequate results and conclusions that present that the energy and speed metrics of the text similarity calculations can be improved thanks to the hardware accelerator. Consequently, the cluster of FPGA-enabled nodes is proposed for the large scale processing.

Implementation of a System for Fast Text Search and Document Comparison

This chapter presents an architecture of the system for fast text search and documents comparison with main focus on N-gram-based algorithm and its parallel implementation. The algorithm which is one of several computational procedures implemented in the system is used to generate a fingerprint of analyzed documents as a set of hashes which represent the file. This work examines the performance of the system, both in terms of a file comparison quality and a fingerprint generation. Several tests were conducted of N-gram-based algorithm for Intel Xeon E5645, 2.40 GHz which show approximately 8x speedup of multi over single core implementation.

The Regular Expression Matching Algorithm for the Energy Efficient Reconfigurable SoC

This paper presents an algorithm for a regular expressions pattern matching system. The goal was to achieve better performance and low energy consumption. The proposed scheme is particularly useful when a large set of complex regular expression patterns must be inspected in parallel (e.g. in computer malware and anti-virus systems). The idea of the algorithm derives from a concept of the Bloom filter algorithm. The Bloom filter operation is used to inspect an incoming data and to find static sub-patterns of regular expressions. When the Bloom filter reports a match, a closer inspection is performed. The Bloom filtering is done by a hardware dedicated co-processor. The regular expressions’ wildcard matching part is executed by a CPU.