Takashi Eshita

Development of sub 10-µm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory

200-mm and 300-mm device wafers were successfully thinned down to less than 10-µm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-µm, switching charge showed no change by the thinning process. CMOS logic device wafers thinned to 7-µm indicated neither change in Ion current nor junction leakage current. Thinning such wafers to <10-µm will allow for lower aspect ratio less than 4 of Through-Silicon-Via (TSV) in a via-last process.

Development of ferroelectric RAM (FRAM) for mass production

We have developed ferroelectric capacitor fabrication technique and a new sensing amplifier circuit to realize low-voltage and high-density FRAM. Improvement of IrO, top electrode near the ferroelectric interface successively lowers operation voltage. And our developed “Dual Reference Sensing Amplifier” enables to commercialize highly-reliable FRAM with memory density of 4Mb or larger.

Fully functional 0.5-/spl mu/m 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique

0.5 /spl mu/m design rule embedded 64 kbit SBT (SrBi/sub 2/(Ta,Nb)/sub 2/O/sub 9/) FeRAMs (ferroelectric RAM) are fabricated using a new low temperature SBT deposition technique. The developed deposition technique has successfully lowered SBT crystallization temperature from 800/spl deg/C to 700/spl deg/C, resulting in co-fabrication of FeRAM and fine CMOS logic devices with W plugs. The fabricated devices are proven to be fully functional.

An X-ray mask using Ta and heteroepitaxially grown SiC

Abstract We have developed an X-ray mask using Ta as the X-ray absorber and heteroepitaxially grown SiC as the X-ray membrane. Ta was reactive ion etched with a Cl 2 /CCl 4 gas mixture. Because of the high etching selectivity of Ta to a resist, 0.15 μm line and space patterns could be made using a single layer resist as an etching mask. SiC was heteroepitaxially grown on off-axis Si (111) substrates at 1,000°C with a gas mixture of SiHCl 3 /C 3 H 8 /H 2 . The properties were nearly the same as bulk values. The radiation durability was greater than 100 MJ/cm 3 . This combination of Ta and SiC is an excellent candidate for use in future X-ray lithography.

Direct deposition of SrBi2Ta2O9 Film on IrO2 electrode using liquid source CVD method

Abstract SrBi2Ta2O9 (SBT) thin films were directly deposited on IrO2 electrode using liquid source CVD (LS-CVD) method. Bi deficient region in the SBT films, which existed near the conventional Pt bottom electrode, was successfully eliminated using IrO2 bottom electrode. X-ray diffraction analysis showed our SBT films on IrO2 have good crystalline quality. Satisfactory electric properties (6 μC/cm2 of 2Pr and 10−6 A/cm2 of leakage current) were obtained

Realization of highly resistive GaAs/Si interface and improvement of RF performance for high electron-mobility transistors grown on Si substrates

InGaP/InGaAs pseudomorphic high electron-mobility transistors (HEMTs) were fabricated on highly resistive GaAs-on-Si substrates. To improve the RF performance of HEMT/Si, the conductive layer at the GaAs/Si interface was suppressed by using H2-preheating instead of AsH3-preheating and by adding a low-temperature-grown AlGaAs layer near the interface. A high sheet resistance of 10–20 k Ω/sq. was obtained for the GaAs-on-Si substrate. By preventing the parasitic effects, the S-parameters of the HEMTs/Si were improved and a maximum frequency of oscillation (fmax ) of 85 GHz was achieved.

Control of La-doped Pb(Zr,Ti)O3 crystalline orientation and its influence on the properties of ferroelectric random access memory

We investigated the crystallization mechanisms of sputter-deposited La-doped Pb(Zr,Ti)O3 (PLZT) on a Pt/Ti metal stack in the postdeposition annealing (PDA) at 600 °C in O2-mixed Ar ambient. As-deposited amorphous PLZT generally transforms to a perovskite phase over 550 °C through a metastable pyrochlore phase during the PDA. We found that the O2 content of the PDA ambient crucially affects the pyrochlore-perovskite transformation (PPT) speed. While an O2 content much higher than 2% of the PDA ambient suppresses PPT, an O2 content much lower than 2% enhances PPT. An O2 content around of 2% of the PDA suppresses PPT near the surface of PLZT and simultaneously keeps PPT fast in the inner regions of PLZT in the pyrochlore phase because of the O2 diffusion limit from the PLZT surface, eventually resulting in almost only the growth of highly {111} oriented columnar PLZT on Pt, which reveals better electric properties than those obtained by the PDA with the ambient of O2 contents much higher or lower than 2%.

A Triple-Protection Structured COB FRAM with 1.2-V Operation and 1017-Cycle Endurance

We have developed a ferroelectric RAM (FRAM) with a low operation voltage of 1.2 V and a high switching endurance up to 1017 cycles. Our newly developed triple-protection structured cell array, has constructed without an additional mask step, effectively protects 0.4-μm2 ferroelectric capacitors from hydrogen and moisture degradation. We have designed our capacitor-over-bit-line (COB) structure to have a small cell size of 0.5 μm2.

A new 1T/2C merged two-terminal gain cell with SBT encapsulated floating gate MOSFET for highly scalable FeRAM

We fabricated a new scalable gain cell that consists of one transistor (1T) and two ferroelectric capacitors (2C), and can select one individual cell using only two wires. The cell features an encapsulated floating gate MOSFET using SBT film and overlapped capacitors between the wire and the gate, thereby enabling simple high-level integration applicable for Gbit FeRAM. The fabricated prototype devices exhibit successful operation. The cell can write data at 5 V and read data at 2 V nondestructively, and retain data for 5000 s.

Novel pseudomorphic structure on Si substrate grown by metalorganic vapor phase epitaxy

Abstract We propose a novel pseudomorphic InGaAs channel selectively doped structure grown on Si substrates and investigate its characteristics. The proposed structure consists of a Si-doped strained layer superlattice (SLS), an InGaAs channel layer, an SLS buffer layer, and a GaAs buffer layer. We investigated the SLS structure dependence of mobility. The mobility was enhanced by the reduction of the threading dislocation density. We compared the characteristics of high electron mobility transistors (HEMTs) fabricated using the epitaxial structures and conventional structures processed with thermal cycle annealing (TCA). The HEMTs with the proposed structure showed better characteristics than those processed by TCA, indicating the efficiency of the structure.