Kazuhiko Tsuji

A 2Kx8-bit static MOS RAM with a new memory cell structure

A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA.

A 2K×8-bit static RAM

High density 2K×8-bit fully static RAM has been developed. Memory cell size of 23×27µm results in the chip size of 3.75×4.19mm, which is nearly equal to that of existing 4K-bit static RAMs. High packing density is realized by layout of 3µm photolithography and double-level polysilicon process permitting fabrication of memory load resistors upon driver MOSFETs.

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8- mu m double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit. >