Takashi Ohzone

Numerical analysis of alpha-particle-induced soft errors in SOI MOS devices

Alpha-particle-induced soft errors in SOI MOSFETs are examined using a three-dimensional device simulation. A bipolar mechanism induced by the alpha-particle incidence is investigated in detail when an alpha particle penetrates from the drain region toward the source region. In SOI MOSFETs, the drain collected and source injected charges are mainly due to a bipolar mechanism. The bipolar mechanism in SOI MOSFETs is quite different from that which has been so far reported in bulk MOSFETs, and operates with a very small current of less than 1 nA for a very long time of 1 ns to 100 ms. The drain collected and source injected charges are strongly dependent on various device parameters and lifetimes. The results suggest that the bipolar mechanism is a significant cause of soft errors in SOI MOSFETs. >

Fowler–Nordheim tunneling in MOS capacitors with Si-implanted SiO2

Abstract The gate current density ( J G )–voltage ( V G ) characteristics of MOS capacitors with 50xa0nm thick SiO 2 and various Si-implanted doses from 10 13 to 3×10 16 xa0cm −2 have been studied under inversion- and accumulation-conditions. The conduction mechanism is discussed by making use of Fowler–Nordheim (F–N) and Poole–Frenkel (P–F) plots of the J G – V G characteristics with/without a cyclic stress test. The F–N plot for samples without cyclic stress has a linear region which implies the F–N current mechanism. The tunneling barrier height Φ B calculated from the slope of the F–N plots begins to decrease beyond a dose of 10 14 xa0cm −2 . The cyclic stress test of the Si-implanted samples gives saturated hysteresis J G – V G curves, which depend on the implantation condition. Since the P–F plot has a linear region, the P–F current is dominant in the samples with a cyclic stress for | J G |>10 −7 xa0A/cm 2 . The direct tunneling electron/hole current between inversion/accumulation layers in p -Si substrate and traps in SiO 2 may be responsible for a J G value under 10 −7 xa0A/cm 2 , owing to the fact that J G has a hysteresis characteristics and that no linear region exists in either F–N or P–F plot.

Electroluminescence of MOS capacitors with Si-implanted SiO2

Abstract Electroluminescence (EL) characteristics of n + -polysilicon MOS capacitors with 50 nm Si-implanted SiO 2 were measured. The EL intensity is almost proportional to the gate current, and the EL efficiency is about 50–70 times larger than that of a MOS capacitor without Si-implantation. Although the EL spectra of MOS capacitors have a broad peak around 650 nm regardless of the Si-implantation, only the EL intensity of Si-implanted MOS capacitors increases gradually below 500 nm. The latter may be caused by radiative electron capture into two kinds of SiO 2 trap levels, 2.0–2.5 and 3.0 eV below the conduction band of SiO 2 .

Erase/write cycle tests of n-MOSFETs with Si-implanted gate-SiO/sub 2/

To discuss the applicability of a MOSFET with Si-implanted gate-SiO/sub 2/ of 50 nm thickness to a non volatile random access memory (NVRAM) operating more than 3.3/spl times/10/sup 15/ erase/write (E/W) cycles, E/W-cycle tests were performed up to 10/sup 11/ cycles by measuring the hysteresis curve observed in a source follower MOSFET in which a sine-wave voltage of 100 kHz was supplied to the gate. Degradations in the threshold-voltage window of 15 V and gain factor were scarcely observed in a MOSFET with Si-implantation at 50 keV/1/spl times/10/sup 16/ cm/sup -2/ at a gate voltage of /spl plusmn/40 V. Those degradations observed in a MOSFET with 25 keV/3/spl times/10/sup 16/ cm/sup -2/ were improved by lowering the gate voltage from /spl plusmn/40 V to /spl plusmn/30 V in sacrificing the smaller threshold-voltage window from 20 to 8.5 V.

Study of the current–voltage characteristics in MOS capacitors with Si-implanted gate oxide

The specific gate current density (JG) versus voltage (VG) characteristics of MOS capacitors with 50 nm thick, implanted SiO2 (using various Si doses between 10 13 and 3 10 16 cm ˇ2 ) have been studied under inversion and accumulation conditions. From an analysis of dynamic resistance and current humps in the JG‐VG characteristics of the above devices, a qualitative model of the conduction mechanism has been proposed. Major current components in the model are the following: a direct tunnel current of electrons and holes related to traps generated by Siimplantation, a charging current of electrons and holes to traps distributed a little inside the gate oxide, a trapassisted current and a Fowler‐Nordheim tunnel current. The model can explain the JG‐VG curves and the change of the JG‐VG characteristics on the basis of the Si atomic distribution in the gate oxide. # 1999 Elsevier Science Ltd. All rights reserved.

Transient latchup characteristics in n-well CMOS

Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n/sup +/-p/sup +/ spacing L longer than 8 mu m, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 mu m. >

Numerical simulation of single event latchup in the temperature range of 77-450 K

In this paper, the temperature dependence of single event latchup in CMOS structures is studied over a temperature range of 77-450 K through two-dimensional device simulation with full-temperature models. Single event latchup immunity first increases as the temperature decreases from 450 K to 120 K, and then decreases rapidly with further decrease in temperature. Therefore, superior latchup immunity can be expected at about 120 K. Furthermore, latchup immunity at 77 K is almost equal or somewhat inferior to that at room temperature. It can be predicted from our results that CMOS devices become extremely susceptible to single event latchup at temperatures below 77 K just as they do at very high temperatures. >

A self-aligned retrograde twin-well structure with buried p/sup +/-layer

A self-aligned retrograde twin-well structure with a buried p/sup +/-layer surrounding the n-well is presented. The retrograde twin well and buried p/sup +/-layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions, and the channel stop processes are eliminated by using tight spatial distributions of retrograde n- and p-wells. This simple process is compatible with both local oxidation of silicon (LOCOS) and trench isolation processes and allows a scalable CMOS structure for very tight n/sup +/-to-p/sup +/ spacing. The present CMOS structure provides high latchup immunity at 1.5- mu m n/sup +/-to-p/sup +/ spacing and good isolation characteristics without additional n- and p-channel stop dopings. >

Direct-current and alternating-current electroluminescence of MOS capacitors with Si-implanted SiO2

Abstract The direct-current and alternating-current electroluminescence (d.c.- and a.c.-EL) characteristics of n+-polysilicon MOS capacitors with 50xa0nm Si-implanted SiO2 have been measured to discuss EL stability and frequency response. While the d.c.-EL intensity increases with time t at small constant current density (JG) and decreases for large JG, it decreases with t monotonously under constant gate voltage (VG) condition. The time dependence of the d.c.-EL intensity has been modeled with two kinds of states in the oxide layer. The a.c.-EL intensity for samples with various Si implantation conditions increases with frequency except for samples without Si implantation or with low energy implantation. The above implies that Si implantation produces slow states near the oxide–Si interface. A.c.-operation remarkably improved the EL intensity and time dependence. It may be attributed to an increase of effective current due to charge stored under alternating bias conditions.

Electrical characteristics of scaled CMOSFET's with source/drain regions fabricated by 7/spl deg/ and 0/spl deg/ tilt-angle implantations

The differences of electrical characteristics in trench-isolated n-well CMOSFETs with LDD- and EPS-regions fabricated by 7/spl deg/ and 0/spl deg/ tilt-angle phosphorous implantations are measured and qualitatively explained. The CMOSFETs have channel lengths ranging from 5 to 0.4 /spl mu/m and a channel width of 10 /spl mu/m. The differences in impurity profiles due to the channeling ions by 0/spl deg/-implantation cause the clear changes in the punchthrough-current characteristics and the substrate bias-voltage dependences of threshold voltages for both n- and p-MOSFETs. Meanwhile n- and p-MOSFETs fabricated by 7/spl deg/ and 0/spl deg/ implantations show nearly the same characteristics of threshold voltages and subthreshold swings which are almost determined by the impurity profiles in each channel region because the impurity profiles are scarcely affected by the channeling ions. >