Toshiki Arai

Proposal of buried metal heterojunction bipolar transistor and fabrication of HBT with buried tungsten

We propose a buried metal heterojunction bipolar transistor (BM-HBT), in which buried metal in the collector layer could reduce the total base-collector capacitance. To show the possibility of making a BM-HBT, we fabricated an InP-based HBT with buried tungsten mesh replacing the subcollector layer, where tungsten mesh works as a Schottky collector electrode. A flat heterostructure on the InP collector layer of the buried tungsten mesh was confirmed by a cross-sectional SEM view. A DC current gain of 12 was measured from the common-emitter collector I-V characteristics.

C/sub BC/ reduction in GaInAs/InP buried metal heterojunction bipolar transistor

We fabricated GaInAs/InP based buried metal heterojunction bipolar transistors (BM-HBTs), in which a tungsten stripe with the same area as the emitter was buried with an intrinsic collector layer. In this device, there was no conductive layer under the extrinsic base region to reduce the total base-collector capacitance (C/sub BCT/). Though tungsten was embedded in an active region of HBTs, flat surface of base layer and no void formation around buried tungsten were confirmed by the observation of cross section. C/sub BCT/ of 10.3 fF was calculated from Y/sub 12/ parameters and an effective base-collector junction area of BM-HBT was estimated at 22% of conventional-HBT.

Toward nano-metal buried structure in InP – 20 nm wire and InP buried growth of tungsten

Abstract Toward nano-metal buried structure in InP, we studied the fabrication process of nano-tungsten wire and the InP buried growth of tungsten stripes. A tungsten wire with a 20 nm width was fabricated by the proposed metal-stencil liftoff, in which gold/chromium and SiO 2 replace resist to prevent thermal deformation in a conventional liftoff process. The buried growth of tungsten stripes with 1 μ m widths and 2 μ m pitch by organometallic vapor phase epitaxy (OMVPE) was studied. Tungsten stripes were buried under the flat InP layer of 1.1 μ m thickness, and the ratio of grown InP thickness to buried tungsten width was about 1.

Reduction of Base-Collector Capacitance in Submicron InP/GaInAs Heterojunction Bipolar Transistors with Buried Tungsten Wires

A buried metal heterojunction bipolar transistor with a 0.5-µm-wide emitter was fabricated by electron-beam lithography, in which three tungsten wires of 100 nm width, 100 nm height and 200 nm period were buried in the InP collector layer. For the device with an emitter area of 0.5×2.5 µm2, total base-collector capacitance was reduced to about 30% of that calculated from the physical dimensions of a conventional heterojunction bipolar transistor, and a current gain cutoff frequency of 86 GHz and a maximum oscillation frequency higher than 135 GHz were obtained.

First Fabrication of GaInAs/InP Buried Metal Heterojunction Bipolar Transistor and Reduction of Base-Collector Capacitance

We report a novel approach for improving the performance of InP-based heterojunction bipolar transistors (HBTs). A buried-metal heterojunction bipolar transistor (BM-HBT), in which tungsten stripes of the same area as the emitter metal were buried in an i-InP collector layer, was fabricated for the first time. The aim in fabricating this structure is to realize a reduction in the total base-collector capacitance (CBCT). In the measurement of microwave S-parameters, CBCT of 10.3 fF was evaluated. The effective base-collector junction area of the BM-HBT was estimated to be 22% that of conventional-HBT considering the difference in collector thickness.

Fabrication of InP/GaInAs Double Heterojunction Bipolar Transistors with a 0.1-µm-Wide Emitter

InP/GaInAs double heterojunction bipolar transistors (DHBTs) with a 0.1-µm-wide emitter along the direction were fabricated by the self-aligned process. A DC current gain of β=51 as a maximum value was observed. Current amplification was confirmed even when an emitter current was 1 µA. A 0.1-µm-wide emitter was formed by the combination of CH4/H2-reactive ion etching and two kinds of wet etching based on HCl. To our knowledge, this HBT has the narrowest emitter that has ever been reported.

GaAs buried growth over tungsten stripe using TEG and TMG

We studied the buried growth of a GaAs layer over a tungsten stripe using organometallic vapor-phase epitaxy. Triethylgallium (TEG) and trimethylgallium (TMG) were used as group III sources. For growth without polycrystal-like deposition on tungsten surface, the required growth temperature using TMG was lower than that using TEG. For 2-μm-thick growth over a 1-μm-wide tungsten stripe, the flatness of the surface grown using TMG was better than that using TEG. Therefore, the migration length of TMG on tungsten and GaAs must be longer than that of TEG. For a heterojunction bipolar transistor with a tungsten stripe as the collector electrode, a 70-nm-wide tungsten stripe was buried under a 0.77-μm-thick layer of GaAs with a flat surface using TMG. A current gain of 4 was measured although the active region was grown over tungsten stripe.

Evaluation of base-collector capacitance in submicron buried metal heterojunction bipolar transistors

l. Introduction Reduction of base-collector capacitance (csc) is essential for high-speed operation of heterojunction bipolar transistors. Usually reduction of Csc is evaluated by increase of maximum oscillation frequency (fiuail. Thuso decrease of intrinsic Cnc (Cscin) becomes most important [1]. However, future scaling of HBT [2] requires reduction of total Css (Cncr) for increase of cutoff frequency (h). Moreover, smaller cscr provides smaller feedback capacitance, results in larger maximum available gain [l]. In this report, we describe base-collector capacitance in submicron buried metal heterojunction bipotar transistors (BMHBT)[3], which is our proposed structure for reduction of Cscr. When emitter width is 0.3 pm, Cscr was less than lfF. To oru knowledge, this is smallest Cncr in HBT.

Fabrication of InP DHBTs with 0.1 /spl mu/m wide emitter

InP based double heterojunction bipolar transistors (DHBTs) with emitter width of 0.1 /spl mu/m are reported. Emitter mesa with vertical facet was formed by combination of CH/sub 4//H/sub 2/ reactive ion etching (RIE) and wet etching using two different HCl based solutions. Self-aligned base electrode was formed with 0.1 /spl mu/m thick InP emitter layer, by control of the lateral extent of undercut etching of less than 0.1 /spl mu/m.