Kazumasa Tanida

Ultra-high-density interconnection technology of three-dimensional packaging

Abstract The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.

High-performance vertical interconnection for high-density 3D chip stacking package

The three-dimensional (3D) chip stacking technology developed in ASET is a leading technology for realization of a high-density and high-performance system-in-package (SIP). As for the advanced interconnection technology, a 20-/spl mu/m-pitch low impedance vertical interconnection through Cu through via (TV) within thin chips plays the following roles: wide signal bus and very short electrical path for high-frequency signal transmission, strong power supplies and stable ground lines. The vertical interconnection was fabricated by inter chip connection (ICC) process, which includes Cu bump bonding (CBB) utilizing Cu-Sn diffusion for connecting Cu TVs without the formation of bumps on the chip back surface and encapsulation micro thin gap between chips. We elucidate the Cu-Sn diffusion phenomena and Cu oxide influence which were important CBB issues to realize the minute interconnection of Cu TVs. The temperature cycling test (TCT) was performed on chip on chip (COC) and 3D chip stacking structures fabricated by ICC process, and over 1,000 cycles reliability was confirmed. The consistent fabrication of vertical interconnection was realized. Then, we conducted the two important electrical evaluations. One is the DC resistance of the vertical interconnection, which measured only 15.4 m/spl Omega/ per layer. Another was the signal transmission delay, and only 0.9 ps was confirmed. Therefore, the vertical interconnection with Cu TV and ICC demonstrates the excellent capability of high performance interconnections on 3D chip stacking package. In addition, the micro scale strip line was evaluated to realize advanced SIP. The eye diagram on 3 Gbps indicated sufficient transmission. We will be able to realize high performance advanced SIP utilizing the vertical interconnection and high-speed horizontal line.

Micro Cu Bump Interconnection on 3D Chip Stacking Technology

The three-dimensional (3D) chip stacking LSI technology under development at the Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology to realize high-density and high-speed transmission, and superfine flip-chip bonding technologies in 20-µm-pitch microbumps on Cu through-via (TV) are substantial technologies. As for advanced bonding technology, Cu bump bonding (CBB) utilizing Sn alloy is a simple process to connect Cu TVs directly without the formation of bumps on the device back surface, and the influence of the intermetallic compound (IMC) on the minute interconnection focusing on the bondability and reliability was verified, and the following results were obtained. The IMC state formed at the bonding interface depended on bonding temperature, and was confirmed as multilayered Cu6Sn5 and Cu3Sn at 240°C, and single-layered Cu3Sn at 350°C. The IMC state is the governing factor of bondabilities of Cu bump interconnection in a 20-µm-pitch. The electroresistance value of the Cu bump interconnection was approximately 0.45 Ω, and no significant difference was confirmed under each condition. Youngs modulus values of IMC (Cu6Sn5:112.6 GPa and Cu3Sn:132.7 GPa) were obtained by the nano-indentation test. The Sn-Ag layer as bonding material should be reduced to Cu-Sn IMC, and a low-rigid resin was preferable in terms of interconnection reliability based on the results of finite element method (FEM) analysis. Finally, the vertical interconnections utilizing CBB were formed, and the increase in electrical resistance by stacking one TV chip was approximately 0.03 Ω. Therefore, sufficient electrical vertical interconnection of Cu TV in a 20-µm-pitch was performed.

Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 µm Pitch

Superfine flip-chip bonding technologies in 20 µm pitch microbumps on copper through-hole electrodes are substantial technologies for three-dimensional (3D) chip stacking LSI. As the advanced interconnection technology to connect the through-hole electrodes at low temperature and low bonding force, the ultrasonic flip-chip bonding (UFB) was verified by the total evaluation and the atomic-level analysis of the bonding interface on the chip-on-chip (COC) structure utilizing electroplated Au microbumps in 20 µm pitch. First, the lower limit bonding conditions were confirmed to be a bonding force of 20 N and an amplitude of 3 µm; the bonding accuracy achieved was within ±2 µm, the electrical interface resistance was stable about 0.57 Ω, and no damage around the interconnection structure was observed. Secondly, the mechanism of solid phase bonding interface formation at the atomic level without solid phase diffusion was confirmed as the Au-Au solid phase UFB bonding mechanism, and the orientation geometry of such bonding was apparently different from that of thermo compression bonding, which showed solid phase diffusion across the boundary. The achievement of this research will enable the realization of the 3D chip stacking LSI in the near future, which is characterized by scalabilities and high-performance. The subjects are the elucidation of the real oscillation contributes to bonding to optimize the process conditions and the establishment of the micro joint reliabilities utilizing UFB process.

Chip Scale Camera Module (CSCM) using Through-Silicon-Via (TSV)

No one doubts that Through Silicon Via (TSV) is one of the necessary technologies for three-dimensional integration of LSIs. Heterogeneous system integration is a good candidate for its application, which includes the “Vision Chip” [1]. TSV technology is applied to a CMOS imager sensor camera module for mobile handsets and successfully achieves a size reduction of 55% in volume and 36% in footprint, which we refer to as a Chip Scale Camera Module (CSCM). To the best of our knowledge, CSCM is the first mass-produced product using TSV technology.

Ultra-high-density 3D chip stacking technology

The 3D chip stacked LSI technology under development in ASET is a new packaging technology to realize highdensity and high-speed transmission. Two key technologies is necessary to realize the 3D chip stacked LSI. One is low temperature simple interconnection of Cn through electrodes in 20 pm pitch. Other is encapsulation of super narrow gap less than 10 pm between devices. The Cu bump bonding (CBB) process utilizing Sn capped Cu Bump was evaluated, and connection at 245°C and 150T by formation of the inter metallic compound (IMC) as qCu&n5 was confumed. The post aging process was applied to form the complete diffusion layer between Cn bumps after bonding, and the IMC layer was only consist of E-Cu,Sn, and considered to be stable against the thermal stress after chip stacking process. In addition, the non-conductive particle paste (NCP) preform process was evaluated. The micro thin gap was almost encapsulated without void. ,Moreover the chip backside warpage after bonding was very small less than 3 pm, and considered to realize stacking chip onto the stable bonding area. Finally, The mechanical sample of 3D chip stacked module with Cu through electrodes in 20 pm pitch was build snccessfidly utilizing CBB and NCP preform process.

Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

The three-dimensional (3D) chip stacking LSI technology under development in Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology for realizing high-density and high-speed transmission, and superfine flip-chip bonding technologies utilizing 20-µm-pitch micro bumps on Cu through hole electrodes are substantial technologies. There are two key technical issues involved in realizing the 3D chip stacking LSI. One is the provision of the sufficient interconnections, which have low resistivity and which are absolutely connected. Another is the reduction of the thermal stress of the micro bumps by providing encapsulated resin between devices. Regarding the metallurgically stable and low electrical resistance interconnections, electroplated Au bump bonding in 20-µm-pitch by thermo compression bonding process was evaluated on the chip-on-chip(COC) structure. First, the softening of the Au bump by annealing was confirmed, and was expected to decrease the bonding stress of the under bump structure. Second, the lower limit bonding conditions were confirmed to be a bonding force of 24.5 N at 350°C, and the electrical resistance was confirmed to be stable at about 0.55 Ω. The mechanism of Au–Au thermo compression bonding with the solid phase diffusion across the boundary was confirmed. Finally, the life of the 20-µm-pitch interconnection with the underfillresin containing the hyperfine filler particles under temperature cycling tests (TCT) was more than 1000 cycles, which is an acceptable level for a semiconductor package. This research will enable the realization of 3D chip stacking LSI in the near future which features scalability and high performance. The subjects are the verification of the appropriate bump dimensions in order to further improve the reliability and the realization of the interconnection reliability on 3D chip stacking LSI.

Direct wafer bonding technology of 300mm wafer

Recently, direct wafer bonding method is becoming an important technology in the filed of micro electro mechanical system (MEMS), CMOS image sensor and three dimensional (3D) package [1]-[3]. It is well known that the direct wafer bonding method is low cost and pre-bonding at room temperature enables fine aliment accuracy in contrast to the adhesive wafer bonding [4]. However, wafer deformation during bonding and its nonuniformity may cause unexpected stress at the interface and pattern distortion, because the method involves no stress relief layer. Wafer deformation is expected to become severer as the wafer diameter is increased, such as 300 mm wafers. But there are very few studies on wafer distortion, bonding propagation and bonding interface analysis of 300 mm wafer. In this paper, we describe about improvement of distortion by optimizing propagation of bonding front and wafer deformation. Bonding interface was also analyzed to investigate crystal defect by Raman spectroscopy, transmission electron microscopy (TEM), Fast Fourier transform mapping (FFTM) in detail.