Yoshihiko Nemoto

Ultra-high-density interconnection technology of three-dimensional packaging

Abstract The study of 20-μm-pitch interconnection technology of three-dimensional (3D) packaging focused on reliability, ultrasonic flip–chip bonding and Cu bump bonding is described. The interconnection life under a temperature cycling test (TCT) was at an acceptable level for semiconductor packages. Failure analysis and finite element analysis revealed the effect of material properties. Basic studies on ultrasonic flip–chip bonding and very small Cu bump formation were investigated for low-stress bonding methods. The accuracy of ultrasonic flip–chip bonding was almost the same level as that of thermocompression bonding and the electrical connection was also confirmed. Atomic-level bonding was established at the interface of Au bumps. For Cu bump bonding, a dry process was applied for under bump metallurgy (UBM) removal. Electroless Sn diffusion in Cu was investigated and the results clarified that the intermetallic layer was formed just after plating. Finally, we succeeded in building a stacked chip sample with 20-μm-pitch interconnections.

High-performance vertical interconnection for high-density 3D chip stacking package

The three-dimensional (3D) chip stacking technology developed in ASET is a leading technology for realization of a high-density and high-performance system-in-package (SIP). As for the advanced interconnection technology, a 20-/spl mu/m-pitch low impedance vertical interconnection through Cu through via (TV) within thin chips plays the following roles: wide signal bus and very short electrical path for high-frequency signal transmission, strong power supplies and stable ground lines. The vertical interconnection was fabricated by inter chip connection (ICC) process, which includes Cu bump bonding (CBB) utilizing Cu-Sn diffusion for connecting Cu TVs without the formation of bumps on the chip back surface and encapsulation micro thin gap between chips. We elucidate the Cu-Sn diffusion phenomena and Cu oxide influence which were important CBB issues to realize the minute interconnection of Cu TVs. The temperature cycling test (TCT) was performed on chip on chip (COC) and 3D chip stacking structures fabricated by ICC process, and over 1,000 cycles reliability was confirmed. The consistent fabrication of vertical interconnection was realized. Then, we conducted the two important electrical evaluations. One is the DC resistance of the vertical interconnection, which measured only 15.4 m/spl Omega/ per layer. Another was the signal transmission delay, and only 0.9 ps was confirmed. Therefore, the vertical interconnection with Cu TV and ICC demonstrates the excellent capability of high performance interconnections on 3D chip stacking package. In addition, the micro scale strip line was evaluated to realize advanced SIP. The eye diagram on 3 Gbps indicated sufficient transmission. We will be able to realize high performance advanced SIP utilizing the vertical interconnection and high-speed horizontal line.

Ultra-Thin 3D-Stacked SIP Formed using Room-Temperature Bonding between Stacked Chips

The wire bonding technique has been used for conventional 3D-stacked packages. However, it requires an additional bonding area on the substrate and long wires for connecting a chip to a substrate. In this study, a method is described for interconnecting stacked chips using through-hole electrodes. Electrical interconnection between the chips is achieved by simply applying a compressive force at room temperature to a conventional chip with multiple gold stud bumps. The basic concept of the proposed method was validated using test samples with quasi-through-hole electrodes. Application of chip-to-chip interconnection to a conventional 3D-stacked system-in-package (SiP) with an microprocessing unit (MPU) chip and an synchronous DRAM (SDRAM) chip reduced the package thickness to less than 0.5 mm from 1.25 mm and the number of layer in the package substrate to two (thickness less than 0.2 mm) from six (0.45 mm). The wiring distance between stacked chips is minimized by using an interposer chip. We formed through-hole electrodes in a 30-mum-thick silicon wafer and determined that the measured leakage with plasma CVD of SiO2 met our target specification for the electrical insulation between through-hole electrodes. Use of this method should facilitate the production of ultra-slim, high-performance SiP

Advanced packaging technologies on 3D stacked LSI utilizing the micro interconnections and the layered microthin encapsulation

The advanced 3D stacking technologies are discussed in this paper. They are the microbumping in 20 /spl mu/m pitch, the basic processes of the advanced bonding processes for the high precision and the reliable interconnections, the novel technologies to encapsulate the layered microthin gaps less than 10 /spl mu/m, and the non-destructive inspection. These technologies are confirmed to realize the 3D stacked LSI structure, and it will be expanded to the advanced system packaging technologies in the near future.

Fabrication of High-Density Wiring Interposer for 10 GHz 3D Packaging Using a Photosensitive Multiblock Copolymerized Polyimide

We have developed a high-density wiring interposer for 10 GHz 3D packaging using a photosensitive multiblock copolymerized polyimide. This new polyimide can realize micron-sized fine patterns without pattern shrinkage because of the nonrequirement of high-temperature thermal curing. The polyimide has good electric properties such as high breakdown voltage and low dielectric constant. Therefore, it is considered that by introducing this photosensitive polyimide as an insulator of the interposer, a high-performance interposer for LSI packaging can be realized. We confirmed experimentally that the high-density wiring interposer can be fabricated using the polyimide and gold. We optimized the basic properties of the photosensitive polyimide film for the fabrication of the interposer. Fine metal wirings were smoothly covered by the polyimide, as confirmed by scanning electron microscopy (SEM) of the cross section of the fabricated balance pair strip line structure. From the time domain reflectometry (TDR) measurement, it was determined that the characteristic impedance of the strip line is within 55.2 Ω ± 11.5% at the center of the interposer chip.

Cu bump interconnections in 20 /spl mu/m pitch utilizing electroless tin-cap on 3D stacked LSI

The electroless tin-plating on copper has preferable characteristics for thermal compression bonding, although it is easy to decrease in thickness by heating at bonding because of diffusion into the copper. Therefore, the bonding temperature profile was determined to have lower preheating to evaluate the bondabilities with the copper-bumps in 20 /spl mu/m pitch dressed thin tin-caps on each bump. As a result, the possibilities of the interconnections in 20 /spl mu/m pitch were confirmed. The bonding temperature was 300/spl deg/C and the bonding force was 24.5 N. Then, the tin-cap on through-hole electrode (T-COTE) was performed with electroless plating and the basic bonding condition was evaluated on the vertical interconnections. The results showed a sufficient joint between the Cu electrodes through the Si die and the adjacent copper bumps on the interposer. Finally, the results of the feasibilities on the micro-joint at 150/spl deg/C will be discussed in this paper.

Ultra wide bandwidth performance of high-density wiring interposer for 3D packaging

We have demonstrated a high-density wiring interposer for 10 GHz 3D packaging using a photosensitive multiblock copolymerized polyimide. This new polyimide can realize micron-sized fine patterns without the pattern shrinkage because of not requiring high-temperature thermal curing. The polyimide has good electric properties such as high breakdown voltage and low dielectric constant. Therefore, it is considered that by introducing this photosensitive polyimide as an insulator of the interposer, a high-performance interposer for LSI packaging can be realized. We confirmed experimentally that the high-density wiring interposer could be fabricated using the polyimide and the gold metal. From time domain reflectometry (TDR) measurement by using a specially prepared 20-/spl mu/m-pitch microwave contact probe, it was found that the characteristic impedance of the stripline is within 55.2 /spl Omega//spl plusmn/11.5 % at the central 10-mm-square area of the interposer.