Kazunori Furusawa

A 256 Mb multilevel flash memory with 2 MB/s program rate for mass storage applications

A 256 Mb flash memory in 0.26 /spl mu/m CMOS on a 138.6 mm/sup 2/ die uses a multilevel technique. The AND-type memory cell suitable for multilevel operation is used. One sector consists of(8192+256) memory cells. As two bits of data are stored in one physical cell, logical sector size is (16384+512)b. Sector erase and program times are both 1 ms/sector (2048+64B), so typical programming rate is 2 MB/s. By increasing sector size to four times that in conventional two-level flash memories, program throughput is kept acceptable for mass-storage applications, even with multi-level operation.

Yield and reliability of MNOS EEPROM products

MNOS electrically erasable and programmable read-only memory (EEPROM) products have been manufactured using 2- mu m CMOS fabrication technology, in which MNOS memory devices are composed of a 1.6-nm tunnel SiO/sub 2/ layer and a 28-nm Si/sub 3/N/sub 4/ layer. The Hitachi MNOS EEPROM family consists of a 64-kb EEPROM with static random access memory (SRAM) timing and three EEPROM on-chip microcomputers. Electrical and quality tests establish two basic reliability features: ten-year data retention and 10/sup 5/ erase/write cycle endurance. The MNOS EEPROM family yield has reached the same high level as that of SRAM products fabricated with the same 2- mu m CMOS technology. In addition, high-density low-cost MNOS EEPROM products are possible because of the high scalability and high yield attributable to their simple cell structure. >

A 126.6 mm/sup 2/ AND-type 512 Mb flash memory with 1.8 V power supply

A 512 Mb AND-type flash memory in 0.18 /spl mu/m CMOS achieves 126.6 mm/sup 2/ die size, uses a multilevel technique, and adapts to 1.8 V operation. In addition, a read-modify-write mode enables programming free from pre-programmed states.

A 1 Gb multilevel AG-AND-type flash memory with 10 MB/s programming throughput for mass storage application

A 1 Gb multilevel flash memory is fabricated in a 0.13 /spl mu/m CMOS process. The chip area of 95 mm/sup 2/ is achieved using AG-AND-type cells with a multilevel program cell technique and compact write-buffer. By use of constant-charge-injection programming and multi-bank operation, high-speed programming throughput of 10 MB/s achieved.

Improvement of Written-State Retentivity by Scaling Down MNOS Memory Devices

New MNOS retention characteristic phenomena are demonstrated. Shrunk MNOS memory devices are closely evaluated. While charge retentivity of the erased state depends only slightly on silicon nitride thickness, written-state retentivity is improved by reducing silicon nitride thickness. These new phenomena are applied to memory device design. A 1 M bit MNOS EEPROM can be designed with silicon nitride thickness 20.0 nm and programming voltage 10.7 V. These results show the MNOS memory device to be a very promising candidate for Megabit EEPROMs.

A 130-nm CMOS 95-mm 2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput

A 1-Gb AG-AND flash memory has been fabricated using 0.13-μm CMOS technology, resulting in a cell area of 0.104 μm 2 and a chip area of 95.2 mm 2 . By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600μs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

A 126 mm/sup 2/ 4 Gb multilevel AG-AND flash memory with 10 MB/s programming throughput

A 4 Gb flash memory, fabricated in 90 nm CMOS technology, results in a 126 mm/sup 2/ chip size and a 0.0162 /spl mu/m/sup 2//b cell size. Address and temperature compensation methods control the resistance of the inversion-layer local bit-line. A programming throughput of 10 MB/s is achieved by using a self-boosted charge injection scheme.

A 126 mm 2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F 2 of 0.0162μm 2 , resulting in a chip size of 126mm 2 . Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10MB/s.

New Phenomena in MNOS Retention Characteristics and Their Application to Memory Device Design for Megabit EEPROM's

An MNOS memory device design for Meg:abit EEPROM s has been developed. Shrunk MNOS devices are closely evaluated. lThile charge retentivity of the erasedstate depends slightly on SisNa thlckness, written-state retentivity is improved by reducing SigNl thickness. These new phenomena are applied to memory device desiS:n. It is shown that fM bit MNOS EEPROM can be desig:ned with SisN4 thickness 2O. O nm and proS:ranming: voltage 10. ? V. These results show the MNOS device to be a very promising: candidate for Megabit EEpROlf s.