Takaaki Hagiwara

Three-dimensional device simulator Caddeth with highly convergent matrix solution algorithms

A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can he obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFETs can be readily simulated with good convergence and good agreement with experimental results.

A flash-erase EEPROM cell with an asymmetric source and drain structure

A flash-erase EEPROM cell which consists of a single floating gate transistor is described. The cell is based on self-aligned double polysilicon stacked gate structure without a select transistor. It is programmed and erased by hot electrons at the drain edge similar to a UV-EPROM, and by Fowler-Nordheim tunneling of electrons from the floating gate to the source, respectively. An asymmetry in source and drain regions is introduced to enable fast program/erase operation. In addition, an n+concentration in the source region is optimized to achieve reproducible erasure, which is indispensable to avoid over-erasing problem. The optimized cell enables an erasing time of less than one millisecond with 12. 5 V on the source, and a scatter of erased Vth is almost negligible. Endurance and data retention characteristics is also adequate for implementation in memory chips. The small cell area of 9.3µm2is accomplished in a 0.8µm technology.

Yield and reliability of MNOS EEPROM products

MNOS electrically erasable and programmable read-only memory (EEPROM) products have been manufactured using 2- mu m CMOS fabrication technology, in which MNOS memory devices are composed of a 1.6-nm tunnel SiO/sub 2/ layer and a 28-nm Si/sub 3/N/sub 4/ layer. The Hitachi MNOS EEPROM family consists of a 64-kb EEPROM with static random access memory (SRAM) timing and three EEPROM on-chip microcomputers. Electrical and quality tests establish two basic reliability features: ten-year data retention and 10/sup 5/ erase/write cycle endurance. The MNOS EEPROM family yield has reached the same high level as that of SRAM products fabricated with the same 2- mu m CMOS technology. In addition, high-density low-cost MNOS EEPROM products are possible because of the high scalability and high yield attributable to their simple cell structure. >

Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms

A practical three-dimensional device simulator CADDETH (Computer Aided Device DEsign in THree dimensions) has been developed. Matrix solution methods appropriate to three-dimensional analyses have been devised. A vectorization ratio of 97 percent has been attained through efficient use of S-810 super computer with vectorized coding, resulting in a computation speed 16 times greater than can be obtained with S-810 in scalar mode computation. Full avalanche breakdown of MOSFETs can be readily simulated with good convergence and good agreement with experimental results.

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme.<<ETX>>

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 104write/erase cycles.

Device performance degradation to hot-carrier injection at energies below the Si-SiO 2 energy barrier

Device performance degradation due to hot-carriers having energies below the Si-SiO2energy barrier are examined. For a test device with Leff= 0.3 µm and Tox5 nm, transconductance degradation and/or threshold voltage shift have been detected at a drain voltage of 2.5 V, which is lower than the Si-SiO2energy barrier(∼ 3.2 eV). In particular, transconductance degradation, rather than threshold voltage shift, is more noticeable. No sharp cut-off is shown near a drain voltage of 3 V. This transconductance degradation is mainly due to an interface state increase caused by drain avalanche hot-carrier injection. It was also found that the time, τ, that it takes forG_{m} or V_{th}to degrade a certain degree, can be expressed as\tau \propto (1/V_{D})for a VDrange of greater than 2.5 V. This degradation occurs in the same way as for long channel devices at VD> 3 V. Thus, hot carrier-related device degradation may be one of the most stringent problems in submicron MOS FETs, even after the power supply voltage is reduced.

Device performance degradation due to hot carriers having energies below the Si‐SiO2 energy barrier

Device performance degradation due to hot carriers having energies that are below the Si‐SiO2 energy barrier are studied. For a test device with Leff =0.3 μm and Tox =5 nm, transconductance degradation and/or threshold voltage, Vth, shifts are detected at a drain voltage as low as 2.5 V, which is lower than the Si‐SiO2 energy barrier (3.2 eV) for electrons. It is also found that the time τ that it takes for Vth to shift, e.g., 10 mV, can be expressed as τ∝exp(1/VD), in the VD range of greater than 2.5 V. Thus, hot‐carrier‐related device degradation may be one of the most significant problems in submicron metal‐oxide‐semiconductor‐field‐effect transistors, even after power supply voltage reduction.