Kazunori Kanebako
Toshiba
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Publication
Featured researches published by Kazunori Kanebako.
symposium on vlsi circuits | 2007
Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.
IEEE Journal of Solid-state Circuits | 2008
Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai; Menahem Lasser; Mark Murin; Avraham Meir; Arik Eyal; Mark Shlick
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.
international solid-state circuits conference | 2009
Cuong Trinh; Noboru Shibata; T. Nakano; M. Ogawa; Jumpei Sato; Yasuhisa Takeyama; K. Isobe; Binh Le; Farookh Moogat; Nima Mokhlesi; Kenji Kozakai; Patrick Hong; Teruhiko Kamei; K. Iwasa; J. Nakai; Takahiro Shimizu; Mitsuaki Honma; S. Sakai; T. Kawaai; S. Hoshi; Jonghak Yuh; Cynthia Hsu; Taiyuan Tseng; Jason Li; Jayson Hu; Martin Liu; Shahzad Khalid; Jiaqi Chen; Mitsuyuki Watanabe; Hungszu Lin
Today NAND Flash memory is used for data and code storage in digital cameras, USB devices, cell phones, camcorders, and solid-state disk drives. Figure 13.6.1 shows the memory-density trend since 2003. To satisfy the market demand for lower cost per bit and higher density nonvolatile memory, in addition to technology scaling, 2b/cell MLC technology was introduced. Recently, MLC NAND flash memories with more than 2b/cell [1,2] have been reported.
international solid-state circuits conference | 2009
Yan Li; Seungpil Lee; Yupin Fong; Feng Pan; Tien-Chien Kuo; Jongmin Park; Tapan Samaddar; Hao Thai Nguyen; Man L. Mui; Khin Htoo; Teruhiko Kamei; Masaaki Higashitani; Emilio Yero; Gyuwan Kwon; Phil Kliza; Jun Wan; Tetsuya Kaneko; Hiroshi Maejima; Hitoshi Shiga; Makoto Hamada; Norihiro Fujita; Kazunori Kanebako; Eugene Tam; Anne Koh; Iris Lu; Calvin Chia-Hong Kuo; Trung Pham; Jonathan Huynh; Qui Nguyen; Hardwell Chibvongodze
Archive | 2005
Yugo Ide; Kazunori Kanebako
Archive | 2004
Yugo Ide; Kazunori Kanebako; 雄吾 井手; 和範 金箱
Archive | 2012
Noboru Shibata; Kazunori Kanebako
Archive | 1994
Makoto Takizawa; Kazunori Kanebako
Archive | 1992
Kazunori Kanebako
Archive | 2010
Noboru Shibata; Kazunori Kanebako
