Hiroshi Maejima
Toshiba
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Publication
Featured researches published by Hiroshi Maejima.
symposium on vlsi circuits | 2007
Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same design rule. New programming method achieves 0.62 MB/s programming throughput.
IEEE Journal of Solid-state Circuits | 2008
Noboru Shibata; Hiroshi Maejima; Katsuaki Isobe; Kiyoaki Iwasa; Michio Nakagawa; Masaki Fujiu; Takahiro Shimizu; Mitsuaki Honma; Satoru Hoshi; Toshimasa Kawaai; Kazunori Kanebako; Susumu Yoshikawa; Hideyuki Tabata; Atsushi Inoue; Toshiyuki Takahashi; Toshifumi Shano; Yukio Komatsu; Katsushi Nagaba; Mitsuhiko Kosakai; Noriaki Motohashi; Kazuhisa Kanazawa; Kenichi Imamiya; Hiroto Nakai; Menahem Lasser; Mark Murin; Avraham Meir; Arik Eyal; Mark Shlick
A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm design rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same design rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.
IEEE Journal of Solid-state Circuits | 2006
Takahiko Hara; Koichi Fukuda; Kazuhisa Kanazawa; Noboru Shibata; Koji Hosono; Hiroshi Maejima; Michio Nakagawa; Takumi Abe; Masatsugu Kojima; Masaki Fujiu; Yoshiaki Takeuchi; Kazumi Amemiya; Midori Morooka; Teruhiko Kamei; Hiroaki Nasu; Chi-Ming Wang; Kiyofumi Sakurai; Naoya Tokiwa; Hiroko Waki; Tohru Maruyama; Susumu Yoshikawa; Masaaki Higashitani; Tuan Pham; Yupin Fong; Toshiharu Watanabe
An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.
Archive | 2009
Hiroshi Maejima
Archive | 2011
Hiroshi Maejima; Katsuaki Isobe
Archive | 2009
Hiroshi Maejima; Katsuaki Isobe; Naoya Tokiwa; Satoru Takase; Yasuyuki Fukuda; Hideo Mukai; Tsuneo Inaba
Archive | 2005
Takumi Abe; Hiroshi Maejima; Koichi Fukuda; Takahiko Hara
Archive | 2007
Hiroshi Maejima; Katsuaki Isobe; Takumi Abe; Ken Takeuchi
Archive | 2011
Hiroshi Maejima; Katsuaki Isobe; Hideo Mukai
Archive | 2007
Hiroshi Maejima; Makoto Hamada
