Kazushi Akie

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder ldquoJM (Joint Model)rdquo.

Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing Hardware

This paper covers a multi-functional hardware intellectual property (IP) for the encoding and decoding of digital moving pictures with low power consumption. The IP is mainly intended for mobile products such as cellular phones, digital still cameras (DSCs), and digital video cameras (DVCs). It includes VC-1 functionality for Internet content plus AVC (H.264) functionality for digital television broadcasting and MPEG-4 functionality for TV telephony, and is capable of processing D1-sized moving pictures (720 pixels by 480 lines) in real time at an operating frequency of 54 MHz. In addition, original algorithms employed in the IP reduce power consumption by up to 22%.

A low power and high picture quality H.264/MPEG-4 video codec IP for HD mobile applications

We have developed an H.264/MPEG-4 video codec IP for mobile applications such as digital still cameras (DSCs) and digital video cameras (DVCs) The codec is capable of encoding/decoding HD sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD sized at 54 MHz. The original algorithms employed in the codec realize low power of 64 mW for encoding HD with high picture quality equivalent to JM reference encoder.

Extended variable-length mode coding for enhancement of H.264/AVC

Extended variable-length mode coding (EVLC), which dynamically creates code words for coding modes by taking account of the spatio-temporal correlations, is proposed. Experimental results show that EVLC achieves average bitrate reduction of 2.29% and a maximum bit-rate reduction of 6.84% compared to H.264/AVC with negligible increase in computational time.

An 80 mW dual video-codec SoC for seamless playback of digital terrestrial television and mobile broadcasting services

A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.

Three images blending engine supporting multicolor formats, various color depths with small-gate size and high-quality image for SOC design

A small Color Space Conversion (CSC) block in Video Input/ Output (VIO) architecture can efficiently support both standards: ITU-R BT.601 and ITU-R BT.709 for RGB and YCbCr color format. The design of an arbitrary (programmable) coefficient helps to reduce the size of CSC block. A new dithering technique is implemented to achieve the advantages, high-quality image and no buffer memory, of Error-diffusion algorithm and Ordered algorithm. With a small gate count, VIO can also support effectively 4 different inputs with multicolor format, various color depth. This VIO has been used in a SOC chip for mobile phone. The detail of VIO design is described in this paper1