Motoki Kimura

A linear-logarithmic CMOS sensor with offset calibration using an injected charge signal

A combined linear and logarithmic image sensor is implemented in a 0.35 /spl mu/m 1P3M technology. The pixel is 7.5/spl times/7.5 /spl mu/m/sup 2/ with a 37% fill factor and contains only 4 transistors. Offset calibration in the logarithmic region is realized by using electrical charge injection into the photodiode. The sensor achieves 120 dB DR and the offset calibration reduces the FPN from 13 mV to 5 mV.

A 342mW mobile application processor with full-HD multi-standard video codec

Todays cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec design. Homogeneous multi-core processors are power-consuming and achieving high-throughput is difficult [1]. While dedicated circuits can minimize power consumption, the dedicated decoders and encoders in previous reports [2, 3] have difficulty performing all of the media processing that is indispensable for a modern cellular phone [4]. In this paper, we have integrated a mobile application processor featuring a two-stage-processing video codec, tile-based address-translation circuits, and several audio/visual intellectual property (IP) modules.

A Full HD Multistandard Video Codec for Mobile Applications

A full high-definition (full HD) video codec includes a high-performance stream processing unit to support multiple standards in mobile application processors. The unit performs at 40 Mbps when operated at a 162-MHz clock rate. Implemented in 65-nm CMOS technology, the proposed video codec consumes 176 mW in real-time decoding of H.264 full HD video.

Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture

To solve recent pressing issues regarding satisfying numerous video codec standards and supporting “full-high-definition” (full-HD) (i.e., 1920 pixels by 1080 lines) video on different consumer devices, a multi-standard CODEC IP based on a heterogeneous multiprocessor architecture was developed. To achieve satisfactory performance with low power consumption, operation-specific processors were designed in regards to two types of processing: stream processing and pixel processing. The CODEC uses effectively several dedicated circuits for functions which are unsuitable for those processors. To design the CODEC, we developed a C-language model to check that the architecture worked correctly. The model was also used as a reference for verifying the RTL model. The CODEC can process full-HD videos formatted in H.264, MPEG-2, MPEG-4, and VC-1 at an operating frequency of 162 MHz.

An 80 mW dual video-codec SoC for seamless playback of digital terrestrial television and mobile broadcasting services

A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.