Kazushi Asami

Challenges of high-robustness self-assembly with Cu/Sn-Ag microbump bonding for die-to-wafer 3D integration

We demonstrated surface tension-driven self-assembly of chips with Cu/Sn-Ag microbumps in order to satisfy requirements for both high throughput and high alignment accuracy toward 3D system integration. The chips were singulated with different dicing methods: standard single-cut, precise single-cut, and modified step-cut. The alignment accuracies were compared among the three methods. The chips obtained by modified step-cut were precisely aligned within approximately 2 μm and comparable to that obtained by precise single-cut. By optimizing liquid volumes, the step-cut chips having Cu/Sn-Ag microbumps were accurately self-assembled irrespective of microbump densities. The self-assembled chips were successfully bonded at 280°C by thermal compression. The Cu/Sn-Ag daisy chains indicated good electrical characteristics with a resistance of 35 mΩ/joint.

A Cost Effective Via Last TSV Technology Using Molten Solder Filling for Automobile Application

We propose combined solder-TSVs and microbumpsfor cost reduction of 3-D integration. Conventional via-last TSV technology requires microbump formation. We eliminate the microbump process for low cost 3-D process. In our process, TSVs and microbumps are formed simultaneously with solder. We demonstrate this process by fabricating daisy chain chips with 20-µm-pitch TSVs. The TSVs are 7-µm diameter, 20-µm deep, and a total number of 39,000 per chip. Its electrical characteristics are 1.05 ± 0.64 Ω/TSV (3σ, n=20).

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding

Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-μm-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.