Seiji Fujino

Intelligent power IC with partial SOI structure

In the integration of power devices and control circuits, temperature rise caused by the heat dissipation of power devices and electric interference between power devices and control circuits are important problems. In this report, the following was demonstrated by using the partial silicon-on-insulator (SOI) structure with shielding layers. The partial SOI structure has the Si directly bonded areas where power devices are formed and SOI areas where control circuits are formed. Firstly, the temperature rise was reduced to about a half that in the complete SOI structure, and the latch-up occurrence in the control circuit was prevented by the insertion of shielding layers. Secondly, at the condition of 150° C and 16 V, the normal operation of an intelligent power IC consisting of multichannel power devices and a 1-bit microcomputer was accomplished.

A no-snapback LDMOSFET with automotive ESD endurance

This paper presents a no-snapback lateral double-diffused MOSFET (LDMOSFET), which endures the electrostatic discharge (ESD) requirement for automotive applications under the condition of 15 kV, 150 pF, and 150 /spl Omega/, representing one order of magnitude higher ESD voltage than conventional LDMOS. First, the mixed (circuit and device) mode simulations analyze the typical ESD failure dynamics of the conventional LDMOSFET, correlating the circuit level transient responses and the device level snapback characteristics (i.e., the negative breakdown voltage-current (V-I) characteristics). Then, the mechanism of the snapback is clarified from the aspect of the feedback link between the turn-on of the parasitic bipolar junction transistor (BJT) and the breakdown of the drain n-n/sup +/ diode. Finally, a no-snapback LDMOSFET is experimentally demonstrated that attains the objective ESD endurance.

Silicon Wafer Direct Bonding without Hydrophilic Native Oxides

Silicon wafer direct bonding was accomplished between two surfaces which had no hydrophilic native oxide layers. Prior to bonding, two wafers were dipped in conc-HF solution ( ~49% aq.) to remove the native oxide layers and then immersed in deionized water. The level of bonding was evaluated by X-ray topography, high resolution transmission electron microscopy (HRTEM) and tensile strength measurement. It was found that the bonded wafer pairs were void-free and had good bonding strength. HRTEM observation showed that the crystal lattice was continuous and had only small distortions and precipitates. Spreading resistance (SR) measurement across the interface showed that the electric resistance did not increase at the bonding interface. It is suggested that the OH groups which substitute the F atoms terminated on the small portion of the surface play an important role in this conc-HF-treated bonding.

Silicon Wafer Direct Bonding through the Amorphous Layer

We found that excess water molecules and hydrocarbons, existing in the bonding interface and thought to cause voids, were absorbed in the damaged area of the amorphous layer formed on the surface of the wafer upon direct bonding of silicon wafers, thus making it possible to suppress void formation with relatively low heat-treatment temperature of 600° C for 3 h.

A Single Chip Automotive Control LSI Using SOI Bipolar Complimentary MOS Double-Diffused MOS

Using the example of an air bag controller, a single chip solution for automotive sub-control systems is investigated, by using a technological combination of improved circuits, bipolar complimentary metal oxide silicon double-diffused metal oxide silicon (BiCDMOS) and thick silicon on insulator (SOI). For circuits, an automotive specific reduced instruction set computer (RISC) center processing unit (CPU), and a novel, all integrated system clock generator, dividing digital phase-locked loop (DDPLL) are proposed. For the device technologies, the authors use SOI-BiCDMOS with trench dielectric-isolation (TD) which enables integration of various devices in an integrated circuit (IC) while avoiding parasitic miss operations by ideal isolation. The structures of the SOI layer and TD, are optimized for obtaining desired device characteristics and high electromagnetic interference (EMI) immunity. While performing all the air bag system functions over a wide range of supply voltage, and ambient temperature, the resulting single chip reduces the electronic parts to about a half of those in the conventional air bags. The combination of single chip oriented circuits and thick SOI-BiCDMOS technologies offered in this work is valuable for size reduction and improved reliability of automotive electronic control units (ECUs).

Intelligent power IC for automotive electronics, using trench-dielectric-isolation technology

We developed an intelligent power IC suitable for automotive applications, which integrated CMOS, Bipolar and LDMOS and which was fabricated on 0.65 μm design rule process. This IC employs trench-dielectric-isolation (TD) technology and power device technology that improves the ESD (Electrostatic Discharge) robustness. TD technology employing an SOI (Silicon On Insulator) wafer and deep trench isolation realizes very narrow isolation width with no parasitic device. It enables the easier mixing of various circuits on a single chip with high integration density. The power device technology of improves ESD robustness, enables reduction in the number of protection devices in automotive Electronic control units (ECUs), which connect with the power IC output terminals. Therefore, the intelligent power IC developed here can reduce ECU component numbers and hence ECU size, and is applicable to various kinds of ECUs and smart actuators with high reliability at lower cost.