Yasuhiro Kitamura

MEMS-compatible high-density trench capacitor with ultra-conformal Cu/SiO 2 layers by supercritical fluid deposition

We have successfully fabricated a 3D super-capacitor, which can be integrated with MEMS in a wafer level, using Si trenches (aspect ratio = 53) and ultra-conformal supercritical fluid deposition (SCFD) of Cu/SiO2 layers. Taking advantage of large inner surface area of the trenches, the 3D capacitor exhibited 70 times larger capacitance than a planar one having the same projected area, and low leakage current density (<3.8×10−5 A/cm2) at an electric field of 1.5–2.4 MV/cm. This achievement is brought about by ultra-conformal and void-free coating of a SiO2 layer, having a dielectric constant equivalent to the film by conventional deposition method, and ultra-conformal deposition of Cu on oxide surface, both of which are significant achievements for SCFD. Metal-insulator-metal structure is also feasible using a similar process technology, which will allow us monolithic integration of a power storage element, a power generator and sensors in a single MEMS chip for the purpose of battery-free sensor nodes in sensor network.

Challenges of high-robustness self-assembly with Cu/Sn-Ag microbump bonding for die-to-wafer 3D integration

We demonstrated surface tension-driven self-assembly of chips with Cu/Sn-Ag microbumps in order to satisfy requirements for both high throughput and high alignment accuracy toward 3D system integration. The chips were singulated with different dicing methods: standard single-cut, precise single-cut, and modified step-cut. The alignment accuracies were compared among the three methods. The chips obtained by modified step-cut were precisely aligned within approximately 2 μm and comparable to that obtained by precise single-cut. By optimizing liquid volumes, the step-cut chips having Cu/Sn-Ag microbumps were accurately self-assembled irrespective of microbump densities. The self-assembled chips were successfully bonded at 280°C by thermal compression. The Cu/Sn-Ag daisy chains indicated good electrical characteristics with a resistance of 35 mΩ/joint.

Low temperature conformal silicon dioxide deposition using supercritical fluid for polymer-based MEMS

A novel supercritical fluid deposition method (SCFD) of SiO<inf>2</inf> has been developed for polymer-based MEMS. In order to reduce deposition temperature for the application to polymer-based MEMS process, we selected O<inf>3</inf> as an oxidant in SiO<inf>2</inf>-SCFD. Conformal SiO<inf>2</inf> deposition on Si trenches (aspect ratio 24) at low temperatures (below 200 °C) was achieved, which were acceptable for deposition on polymers. In addition, SiO<inf>2</inf> coating on inner wall surface of microchannels, which was made of polydimethylsiloxane (PDMS), was demonstrated.

PDN impedance analysis of TSV-decoupling capacitor embedded Silicon interposer for 3D-integrated CMOS image sensor system

We have proposed to use the electrostatic capacitance of through-silicon-vias (TSV) in the silicon interposer as the decoupling capacitor. Because the electrostatic capacity of the TSV acts as a decoupling capacitor, it is enabled to decrease the power distribution network (PDN) impedance. Therefore, the dependency to the PDN impedance in the effect of the layout and the shape of the TSV capacitor was analyzed. By introducing the 3-D electromagnetic field simulator, precise PDN impedance analysis was carried out. As a result, TSV functions enough as a decoupling capacitor. PDN impedance of the silicon inter-poser with TSV-decoupling capacitor decrease compared with that of the silicon interposer without TSV. Especially, PDN impedance of the silicon interposer with 200-micrometer pitch TSVs shows PDN impedance without the resonance peak from the low-frequency region to the high frequency area.

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding

Two types of high-throughput and high-precision multichip-to-wafer 3D stacking approaches are demonstrated: one is non-transfer stacking and the other one is transfer stacking. Both the stacking approaches employ a self-assembly technologies using liquid surface tension. In the former stacking scheme, large number of chips having 20-μm-square Cu/SnAg microbumps are directly self-assembled face-down on an interposer wafer, like flip-chip bonding. On the other hand, in the latter stacking scheme, the many chips having the microbumps are self-assembled face-up on a carrier wafer with bipolar electrodes for electrostatic chucking. Then, the latter chips are transferred from the carrier to another interposer in wafer-level processing. The alignment accuracies are evaluated and compared between the two stacking approaches. The resulting daisy chains show good electrical properties comparable to conventional flip-chip bonding.

Transient response characteristics of through silicon via in high resistivity silicon interposer

We investigated the transient response characteristic of through silicon via (TSV) in a high-resistivity silicon interposer. For this investigation, signal ground (SG)-TSV-chain pairs in high-resisitivity silicon (>1000 Ω·cm) were prepared. Various pulse waves (swing: -1.8-0 V or 0-+1.8 V, pulse width: 250 ps-100 ms, duty ratio: 1/1) were applied to a SG-TSV-chain pair by using a pulse generator, and output signal was obtained using a sampling oscilloscope. From the rise and fall time of output signal, it was found that the change in transient response characteristic according to the frequency and voltage of the applied pulse wave was very small. This result demonstrates that the change in TSV capacitance with the input signal is very small and that high-resistivity silicon is effective for high speed signal processing.

3D system simulation study of power integrity using Si interposer with distribution TSV decoupling capacitors

Improvements of power integrity (PI) on high-speed system have been studied from the point view of many structures in huge papers[1][2][3]. In this study, the PI simulation for the A-D mixed 3D stack chip system by TSV is done in many kinds of power sources. We already studied on the interposer with large area MIM capacitor was effective for the 3D system [4][5], that understood as an area structure made lower input impedance ever GHz region. As a result, we can find which the input impedance is related largely with the DeCap TSV distribution pitch. Consideration of approach wiring to distributed DeCap TSVs is the key issue for the better PI performance as the result.