Kazushige Ayukawa

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU

We have developed a dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. The scheme is based on two dynamic changes of SDRAM modes: from active standby to standby and from standby to active standby. It reduces both the operating current and the latency of an SDRAM. An analysis using benchmark programs shows that the developed scheme reduces the SDRAM operating current by 40% and latency by 38% compared to those of standby mode. An SDRAM controller was developed based on this scheme and 0.18 /spl mu/m CMOS technology. The area of the controller is 0.28 mm/sup 2/ and its operating current is 2.5 mA at 1.8 V and 100 MHz.

An access-sequence control scheme to enhance random-access performance of embedded DRAM's

An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAMs. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for regular access in graphics applications. In this paper, we propose an access-sequence control scheme which enhances the random-access performance of embedded DRAMs. Access ID numbers, an access queue register, and a write-data buffer combined with the multibank DRAM enable out-of-sequence access which reduces the page-miss penalty during random access. In the case of four successive accesses, the estimated total access time was, respectively, reduced by up to 38 and 32% for one and two page misses, and for five successive accesses with one or two page misses, it was, respectively, reduced by up to 44 and 45%.