Yoshinobu Nakagome

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

An As-P(n + -n - )double diffused drain MOSFET for VLSI's

An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSIs from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

Crown-shaped stacked-capacitor cell for 1.5-V operation 64-Mb DRAMs

A self-aligned stacked-capacitor cell called the CROWN cell (a crown-shaped stacked-capacitor cell), used for experimental 64-Mb-DRAMs operated at 1.5 V, has been developed using 0.3- mu m electron-beam lithography. This memory cell has an area of 1.28 mu m/sup 2/. The word-line pitch and sense-amplifier pitch of this cell are 0.8 and 1.6 mu m, respectively. In spite of this small cell area, the CROWN cell has a large capacitor surface area of 3.7 mu m/sup 2/ because (1) it has a crown-shaped capacitor electrode, (2) its capacitor is on the data line, and (3) it has a self-aligned memory cell fabrication process and structure. The large capacitor area and a Ta/sub 2/O/sub 5/ film equivalent to a 2.8-nm SiO/sub 2/ film ensure a large storage charge of 33 fC (storage capacitance equals 44 fF) for 1.5-V operation. A small CROWN cell array and a memory test circuit were successfully used to achieve a basic DRAM cell operation. >

A 4.4-ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply.<<ETX>>

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM

This paper describes a 5-GByte/s data-transfer scheme suitable for synchronous DRAM memory. To achieve a higher data-transfer frequency, the properties were improved based on the frequency analysis of the memory system. Then, a bit-to-bit skew compensation technique that eliminates incongruent skew between the signals is described with a new, multioutput controlled delay circuit to accomplish bit-to-bit skew compensation by controlling transmission timing of every data bit. Simulated maximum data-transfer rate of the proposed memory system resulted in 5.1/5.8 GByte/s (321/365 MHz, /spl times/64 bit, double data rate) for data write/read operation, respectively.

Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V/sub CC/ sheath-plate capacitor (HSPC) cell has been developed using 0.6- mu m-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 mu m/sup 2/ and excellent immunity (critical charge Q/sub c/ >

An experimental 220 MHz 1 Gb DRAM

With the arrival of the multimedia era, high-data-rate memory LSIs are becoming increasingly important to keep up with high-speed CPUs, graphics processors, and other consumers of stored data. Video editing and replaying of high-definition television in particular require a high bandwidth. This paper presents two circuit technologies for a synchronously operating high-data-rate 1 Gb DRAM: a distributed-column-control architecture reducing the burst-mode cycle time, and a ringing-canceling output buffer ensuring reliable high-speed data transfer.

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

A distributed-column-control architecture is proposed to reduce the burst-mode cycle time of large-capacity DRAMs. It features independent operation of the I/O block and subarrays, eliminating the wiring delay in the internal buses from the longest pipeline stage. The timing difference between the I/O block and the subarrays is compensated for by event-driven circuits. This architecture also eliminates the timing margin between the activation of column selection lines, reducing the cycle time by 25%. To evaluate this architecture, an experimental synchronously operating 1-Gb DRAM was designed and fabricated using a 0.16-/spl mu/m CMOS process. It operates with a 22O-MHz clock and a 1.5-V power supply.

An experimental single-chip data flow CPU

The HPSm (high-performance substrate) single-chip data flow CPU is described. It enhances throughput by using three function units-two arithmetic and logic units (ALUs) and one memory interface-to exploit parallelism, while executing reduced instruction set computer (RISC) instructions in a data-driven manner to keep the function units busy. By using three function units, it is capable of operating at a peak performance of 30 MIPs while running at 10 MHz. It employs four on-chip smart memories to control data-driven execution on the three function units and to support branch prediction and exception handling. It is implemented in a 1.6-&mu;m double-metal CMOS process. The chip contains 87279 transistors, occupies an area of 13.83 mm&times;13.04 mm, and dissipates 2 W