Kazuya Iwase

A new source optimization approach for 2X node logic

Source mask optimization (SMO) and double patterning technology (DPT) are considered key Resolution Enhancement Technique (RET) enablers for scaling 2x nodes and beyond design rules, using existing 193 nm ArF technology prior to EUV availability. SMO has been extensively shown to enlarge the process margin for critical layers in memory cells and test patterns; however the best SMO flow for a large random logic area up to full-chip application has been less explored. In this study, we investigated how the mask complexity in the source optimization impacts the final process window on a random logic layout after DPT, and proposed a new source optimization approach. Example used is a contact layer for 2x logic designs. The SMO source optimization is performed using the SRAM cells with different mask complexities. These optimized sources are then evaluated based on a large-area random logic layout after mask-only optimization. CD variation through process window is used as the metric for comparison. We found the best result is obtained when the source is optimized with the full flexibility of the source and mask with freeform SRAFs and minimal MRC constraints. The source optimized with this approach can reduce CD variation through process window in the random logic without increasing its mask complexity.

Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).

Alternating phase-shift mask and binary mask for 45-nm node and beyond: the impact on the mask error control

For 45 nm node and beyond, the alternating phase-shift mask (alt. PSM), one of the most expected resolution enhancement technologies (RET) because of its high image contrast and small mask error enhancement factor (MEEF), and the binary mask (BIM) attract attention. Reducing CD and registration errors and defect are their critical issues. As the solution, the new blank for alt. PSM and BIM is developed. The top film of new blank is thin Cr, and the antireflection film and shielding film composed of MoSi are deposited under the Cr film. The mask CD performance is evaluated for through pitch, CD linearity, CD uniformity, global loading, resolution and pattern fidelity, and the blank performance is evaluated for optical density, reflectivity, sheet resistance, flatness and defect level. It is found that the performance of new blank is equal to or better than that of conventional blank in all items. The mask CD performance shows significant improvement. The lithography performance of new blank is confirmed by wafer printing and AIMS measurement. The full dry type alt. PSM has been used as test plate, and the test results show that new blank can almost meet the specifications of pi-0 CD difference, CD uniformity and process margin for 45 nm node. Additionally, the new blank shows the better pattern fidelity than that of conventional blank on wafer. AIMS results are almost same as wafer results except for the narrowest pattern. Considering the result above, this new blank can reduce the mask error factors of alt. PSM and BIM for 45 nm node and beyond.

Progress in proximity electron lithography: demonstration of print and overlay performance using the low-energy electron beam proximity-projection lithography β tool

Shinji OmoriShinichiro NohdoShoji NohamaKoichi NakayamaKazuya IwaseTomonori MotohashiKeiko AmaiYoko WatanabeKazuharu InoueIsao AshidaHidetoshi OhnumaHiroyuki NakanoShigeru MoriyaTetsuya KitagawaSony Corporation4-14-1 Asahi-choAtsugi, Kanagawa, 243-0014JapanE-mail: shinji.omori@jp.sony.comAbstract. The lithographic performance of the low-energy electron-beam proximity-projection lithography (LEEPL)btool is demonstrated interms of printability and overlay accuracy to establish the feasibility ofproximity electron lithography (PEL) for the 65-nm technology node. TheCD uniformity of 5.8 nm is achieved for the 13 stencil mask, and themask patterns are transferred onto chemically amplified resist layers,coupled with a conformal multilayer process with the mask-error en-hancement factor of nearly unity. Meanwhile, the overlay accuracy of27.8 nm is achieved in the context of mix and match with the ArF scan-ner, and it is also shown that real-time correction for chip magnification,enabled by the use of die-by-die alignment and electron beam, can fur-ther reduce the error down to 21.3 nm. On the basis of the printability ofprogrammed defects, it is shown that the most critical challenge to besolved for the application to production is the quality assurance of maskssuch as defect inspection and repair.

Litho-and-mask concurrent approach to the critical issues for proximity electron lithography

The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 mm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.

BEOL process technology based on proximity electron lithography: demonstration of the via-chain yield comparable with ArF lithography

Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm node. Critical comparison between conventional ArF lithography and PEL as to the via-chain yield for test element groups (TEGs) including approximately 2.9 million via chains was performed to demonstrate its production feasibility.

On-site use of 1x stencil mask: control over image placement and dimension

We propose the efficient on-site use of a 1x stencil mask for proximity electron lithography (PEL) for controlling image placement (IP) and critical dimension (CD). It has been demonstrated that the integrated approach to the IP-error correction on the mask-fabrication level using the data manipulation and the mask-exposure level using the deflection of an electron beam (EB) can meet the requirement for the overlay accuracy in the 65-nm technology node. Also, the time-dependent variation in mask CD due to EB-assisted contamination growth can be managed by using the combination of the dose control and the periodic dry cleaning of the mask.

State-of-the-art performance of stencil mask for LEEPL

The critical-dimension (CD) performance and the printability of 1x stencil masks used for low-energy electron-beam proximity-projection lithography (LEEPL) have been studied by using the LEEPL β-tool. The CD uniformity and the line edge roughness on the mask are 6.0 nm and 3.5 nm in 3σ, respectively. It has been found that the fidelity of the etching process is so high that the optimization of the electron-beam writing process is critical to perforate high-quality patterns. The mask error enhancement factor evaluated over 80-100 nm lies is nearly unity, demonstrating the excellent fidelity of image transfer from the mask to a wafer. The critical defect sizes are 14.5 and 22.8 nm for the protrusions on the edges of 100-nm lines and the 150-nm contact holes respectively, implying that defect inspection is a challenge. The current achievements and the final targets in the 65-nm node are compared to assess the gap that must be bridged.

New mask format for low-energy electron-beam proximity projection lithography

In order to solve the various problems associated with a LEEPL mask as originally demonstrated in the form of single-membrane diamond mask, we propose a new mask format termed COSMOS (complementary stencil mask on strut-supports). The COSMOS has small-area membranes with strut reinforcement and is somewhat similar to the masks used for other types of electron projection lithography (EPL). However, the exposure strategy is completely different from the other EPLs; a complete pattern image can be transcribed by overlaying complementary portions of a mask pattern via multiple exposures. The inter-membrane and intra-membrane distortions of image placement have been computed by the finite element method (FEM) simulation. It is concluded that the global distortion induced by the inversion of gravity can be corrected for by mask writing, and the intra-membrane distortion, induced by both the gravitational flexure of a membrane and the pattern density distribution, can be neglected with the membrane intrinsic stress of approximately 5 Mpa..

A new criterion of mask birefringence for polarized illumination

We propose a new criterion for mask birefringence in polarized illumination. Mask birefringence is one of the critical properties of polarized illumination, because the illumination polarization is disturbed by the birefringence of a mask substrate. From this point of view, the allowable mask birefringence has already been analyzed. In these analyses, only the absolute values of birefringence have been specified. As has been pointed out, the mask is a rotation retarder for the polarized illumination. Therefore, the angle of the fast axis of mask birefringence also affects the state of polarization. The new criterion of mask birefringence which we propose here adopts the angle of fast axis as well as the absolute value of birefringence. This new criterion correlates well with the printed critical dimensions (CDs). To demonstrate this, printed CDs were calculated as a function of birefringence. A lithography simulator was used to verify the fit of the new criterion. In this simulation, experimentally measured absolute values of birefringence and the angle of fast axis were used. The simulation showed that there was poor correlation between printed CDs and the absolute values of birefringence. On the other hand, the new criterion exhibited a good correlation with the printed CDs. This difference is attributed to the effect of the angle of fast axis.