Peter De Bisschop

Novel aberration monitor for optical lithography

The aberration monitor allows independent determination of spherical, coma, astigmatism and three point in a single experiment using existing equipment. The monitor consists of a circular phase object, with a diameter of approximately (lambda) /NA and a phase depth of (lambda) /2. Due to the relative large diameter, the image prints as a narrow ring into the resist. Without aberrations its contours are concentric circles. Aberrations deform the ring in a characteristic way. A detailed analysis of the ring shape through focus identifies the aberrations of the projection lens. A linear aberration model is compared with simulations. Experimental results of various aberrations are shown and ar correlated to line width measurements and interferometric lens data.

Impact of high order aberrations on the performance of the aberration monitor

The aberration ring test is used to determine the low and high order lens aberrations. The method is based on two key elements: the linear response of ART to aberrations and the use of multiple imaging conditions. Once the model parameters are determined by means of simulations, the Zernike coefficients are solved from a set of linear equations. The Zernike coefficients thus obtained are correlated to interferometric lens data and to line width measurements.

Validity of the Hopkins approximation in simulations of hyper-NA (NA>1) line-space structures for an attenuated PSM mask

In our previous work we have shown that as the NA of a lithographic projection system increases some of the simulation assumptions that are traditionally made - such as the so-called Hopkins assumption, i.e. the assumption that diffraction at the mask is independent of the angle of incidence of the illuminating light waves - break down, at least in some cases. Reliable simulation results will then only be obtained if this Hopkins assumption is eliminated, i.e. when the diffraction effect is reevaluated for each incident direction. The differences in the results between two such simulations, one using the Hopkins approach, the other with this assumption removed, have been demonstrated to be very significant in some case, but today there is no clear understanding when the removal of the Hopkins assumption is essential: a systematic study is not available. As simulations without the Hopkins approximation are significantly more time consuming than simulations done under the Hopkins assumption, a better understanding of which model can or must be used under which circumstances, would be of significant practical importance. The aim of this paper is to provide such a more systematic study for the case of 6% attenuated PSM with line/space structures targeting at a 45 nm resist linewidth for a variety of pitches, for a NA = 1.2 water immersion system. Standard lithographic metrics such as process windows will be used to compare the two simulation approaches. All this work will be done taking the mask topography and optical material parameters into account. As the polarization state of the mask-illumination will also greatly affect the imaging quality at hyper-NA, we will compare the results for different polarization states and illumination modes.

Rigorous mask modeling using waveguide and FDTD methods: an assessment for typical hyper-NA imaging problems

This paper presents an evaluation of the finite-difference time-domain method (FDTD) and of the waveguide method (WG) for the simulation of typical hyper NA imaging problems. In contrast to previous comparisons of rigorous mask modeling methods, which were restricted to the assessment of few near fields, diffraction efficiencies, or aerial images at fixed imaging configurations, we compare the methods in terms of CPU-time and memory requirements, their capability to predict parameter dependencies and more global lithographic process characteristics such as process windows and through-pitch behavior.

Design compliance for spacer is dielectric (SID) patterning

Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE. This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID. Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.

A new source optimization approach for 2X node logic

Source mask optimization (SMO) and double patterning technology (DPT) are considered key Resolution Enhancement Technique (RET) enablers for scaling 2x nodes and beyond design rules, using existing 193 nm ArF technology prior to EUV availability. SMO has been extensively shown to enlarge the process margin for critical layers in memory cells and test patterns; however the best SMO flow for a large random logic area up to full-chip application has been less explored. In this study, we investigated how the mask complexity in the source optimization impacts the final process window on a random logic layout after DPT, and proposed a new source optimization approach. Example used is a contact layer for 2x logic designs. The SMO source optimization is performed using the SRAM cells with different mask complexities. These optimized sources are then evaluated based on a large-area random logic layout after mask-only optimization. CD variation through process window is used as the metric for comparison. We found the best result is obtained when the source is optimized with the full flexibility of the source and mask with freeform SRAFs and minimal MRC constraints. The source optimized with this approach can reduce CD variation through process window in the random logic without increasing its mask complexity.

Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning

For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.

Simulation of the effect of a resist-surface bound air bubble on imaging in immersion lithography

Resist-surface bound air bubbles have been identified as a possible defect mechanism in immersion lithography. The general expectation is that the bubble will primarily cause local dose reductions, but no detailed simulations on this effect have been published. The work described in this paper is a first attempt to do so: we have simulated the effect of bubbles on 1:1 dense Line/Space patterning. Our results confirm that the major effect of the presence of a bubble is indeed underexposure - or in most cases even non-exposure - of the pattern in the area occupied by the bubble, but it also identifies a few more subtle characteristics of bubble-induced defects which can help identify defects observed on immersion wafers as being caused by a bubble. Apart from the simulation results, we also show a few experimentally observed immersion defects, which we believe are indeed generated by a bubble.

Stochastic effects in EUV lithography: random, local CD variability, and printing failures

Stochastic effects in lithography are usually quantified through local CD variability metrics, such as line-width roughness or local CD uniformity (LCDU), and these quantities have been measured and studied intensively, both in EUV and optical lithography. Next to the CD-variability, stochastic effects can also give rise to local, random printing failures, such as missing contacts or microbridges in spaces. When these occur, there often is no (reliable) CD to be measured locally, and then such failures cannot be quantified with the usual CD-measuring techniques. We have developed algorithms to detect such stochastic printing failures in regular line/space (L/S) or contact- or dot-arrays from SEM images, leading to a stochastic failure metric that we call NOK (not OK), which we consider a complementary metric to the CD-variability metrics. This paper will show how both types of metrics can be used to experimentally quantify dependencies of stochastic effects to, e.g., CD, pitch, resist, exposure dose, etc. As it is also important to be able to predict upfront (in the OPC verification stage of a production-mask tape-out) whether certain structures in the layout are likely to have a high sensitivity to stochastic effects, we look into the feasibility of constructing simple predictors, for both stochastic CD-variability and printing failure, that can be calibrated for the process and exposure conditions used and integrated into the standard OPC verification flow. Finally, we briefly discuss the options to reduce stochastic variability and failure, considering the entire patterning ecosystem.Stochastic effects in lithography are usually quantified through local CD variability metrics, such as line-width roughness or local CD uniformity (LCDU), and these quantities have been measured and studied intensively, both in EUV and optical lithography. Next to the CD-variability, stochastic effects can also give rise to local, random printing failures, such as missing contacts or microbridges in spaces. When these occur, there often is no (reliable) CD to be measured locally, and then such failures cannot be quantified with the usual CD-measuring techniques. We have developed algorithms to detect such stochastic printing failures in regular line/space (L∕S) or contactor dot-arrays from SEM images, leading to a stochastic failure metric that we call NOK (not OK), which we consider a complementary metric to the CD-variability metrics. This paper will show how both types of metrics can be used to experimentally quantify dependencies of stochastic effects to, e.g., CD, pitch, resist, exposure dose, etc. As it is also important to be able to predict upfront (in the OPC verification stage of a production-mask tape-out) whether certain structures in the layout are likely to have a high sensitivity to stochastic effects, we look into the feasibility of constructing simple predictors, for both stochastic CD-variability and printing failure, that can be calibrated for the process and exposure conditions used and integrated into the standard OPC verification flow. Finally, we briefly discuss the options to reduce stochastic variability and failure, considering the entire patterning ecosystem.

Joint optimization of layout and litho for SRAM and logic towards the 20nm node using 193i

This paper reports on a simulation study in which we compare different possibilities to find a litho solution for SRAM and Logic for planar technology nodes between 28 nm and 20 nm, using 193 nm immersion lithography. At these nodes, it becomes essential to include the layout itself into the optimization process. The so-called gridded layout style is an attractive candidate to facilitate the printability of several layers, but the benefit of this style, as compared to less restricted layout styles, is not well quantified for the various technology nodes of interest. We therefore compare it with two other, less restricted, layout styles, on an identical (small) SRAM-Logic test chip. Exploring a number of paths in the layout-style - litho-options search space, we try to quantify merits and trade-offs for some of the relevant options. We will show that layout restrictions are really becoming mandatory for the technology nodes studied in this paper. Other important enablers for these aggressive nodes are multiple patterning, the use of a local-interconnect layer, negative-tone development, SMO and the use of optimized free-form illumination sources (from which we also include a few initial wafer results).