Kazuyasu Nishikawa

Platinum Etching and Plasma Characteristics in RF Magnetron and Electron Cyclotron Resonance Plasmas

The properties of platinum etching were investigated using both rf magnetron and electron cyclotron resonance plasmas, together with measurement of the plasma parameters. Experiments were performed over a wide pressure range from 0.4 to 50 mTorr in Cl2 plasmas. In rf magnetron plasmas, the etch rate of Pt was constant at the substrate temperature from 20 to 160°C. The etch rate and the plasma electron density increased with decreasing gas pressure from 50 to 5 mTorr. In ECR plasmas for rf power of 300 W, the etch rate of Pt was almost constant (~100 nm/min) with decreasing gas pressure from 5 to 0.4 mTorr, while the plasma electron density was gradually increased with decreasing gas pressure. These experimental results were discussed with respect to the relationship between the etch yield and ratio of neutral Cl flux and ion flux incident on the substrate. Submicron patterning (0.5 µm lines & spaces) of platinum masked with photoresist was demonstrated using Cl2 plasmas in ECR discharges. High accuracy was obtained with no undercutting.

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

Characteristics of transmission lines fabricated by CMOS process with deep n-well implantation

We characterized the properties of transmission lines fabricated using a CMOS process with a deep n-well implantation and compared them with the properties of the transmission lines on the silicon substrate with other well formations, e.g., a p-well and those without well formations. The series inductance of the transmission line is nearly constant, for both the various well formations and the resistivities of the silicon substrate. The characteristic impedance of the transmission line on the silicon substrate with the deep n-well is higher than this value on the substrates with the p-well and those without well formations. This is because the capacitance of the transmission line on the silicon substrate with the deep n-well is larger due to the p-n junction. Moreover, the capacitance of the transmission line on the substrate with the deep n-well decreases when the dc bias voltage applied to the deep n-well is increased. The capacitance of the transmission line on the substrate with the deep n-well is nearly constant for the various resistivities of the silicon substrate, while the capacitance of the line on the substrate with the p-well decreases with higher resistivity of the substrate.

A 0.8 dB insertion-loss, 23 dB isolation, 17.4 dBm power-handling, 5 GHz transmit/receive CMOS switch

The highest performance to date of any switch using a CMOS process, with a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz, is accomplished with an optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations, lead to the realization of this low insertion-loss. Moreover, the combined effect of the adoption of the source/drain DC biasing scheme and the high substrate resistance in the DET contributes to the high power-handling capability.

Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters

This paper describes a low-current consumption CMOS comparator using a charge-storage amplifier for A/D converters. A comparator is usually composed of an amplifier and a latch. Because the amplifier consumes higher amounts of current than the latch, the comparator needs a low-current consumption amplifier. In this paper, we propose a new charge- storage amplifier for a low-current consumption comparator. The charge-storage amplifier consumes a constant current only during the charging period to internal capacitors, which are used as load devices instead of transistors or resistors. The comparator was designed and fabricated using a standard logic CMOS technology. Consequently, the charge-storage amplifier consumed less than one-half of the current of a normal amplifier that had transistor loads.

Reduction of crosstalk noise between interconnect lines in CMOS RF integrated circuits

We have numerically investigated crosstalk noise between interconnect lines in CMOS RF integrated circuits. Immersed microstrip line (IMSL) and immersed coplanar waveguide (ICPW) over Si substrate were analyzed to make clear shielding effect of grounded planes to reduce crosstalk noise between parallel interconnect lines. It was shown that the crosstalk between the interconnect lines were extensively reduced by the use of IMSLs or ICPWs, compared with simple lines. However, in layout designs using ICPWs, we need consideration about the transmission loss due to the electromagnetic coupling with the lossy Si substrate. On the other hand, for IMSL configurations, the transmission loss due to the Si substrate is small, because the ground plane shields the signal line from the electromagnetic coupling with the Si substrate.