Yasushi Hashizume

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-/spl mu/m standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q/sub s/) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-/spl mu/m CMOS process. The chip size is 7.9/spl times/16.7 mm/sup 2/ and cell size is 1.35/spl times/2.8 /spl mu/m/sup 2/.

Circuit design techniques for low-voltage operating and/or giga-scale DRAMs

As use of battery-operated machines, such as hand-held computers and PDAs, becomes wider, low-voltage/low-power DRAMs are required. Low-voltage technologies are also required in giga-scale DRAMs with scaled-down voltage. This paper describes low-voltage circuit design techniques to meet these demands.

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-μm CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.

An Electrostatic-Discharge(ESD) Protection Device with Low Parasitic Capacitance Utilizing a Depletion-Layer-Extended Transistor(DET) for RF CMOS ICs

In this paper, an electrostatic-discharge (ESD) protection device for RF complementary metal oxide semiconductor (CMOS) ICs utilizing the Depletion-layer-Extended Transistor (DET) [rf1] is reported. The DET, which reduces the area component of junction capacitance by about 1/3, realizes an ESD protection device with low parasitic capacitance. With transmission line pulse (TLP) testing, the DET demonstrates about the same or higher ESD robustness than the conventional transistor. The junction capacitance of the proposed device for obtaining a failure current (It2) of 1–1.33 A in TLP testing, corresponding to a Human Body Model (HBM) tolerance of 2 kV, is estimated to be very low, less than 150 fF. The proposed ESD protection device is very promising for the realization of high-performance and highly reliable RF CMOS ICs.