Akihiko Furukawa

Low on-resistance 1.2 kV 4H-SiC MOSFETs integrated with current sensor

4H-SiC MOSFETs integrated with a current sensor have been fabricated for the first time. The MOSFET shows superior characteristics with a specific on-resistance of 3.7 mΩcm2 and a blocking voltage of 1.4 kV. The deviation of the current ratio (Imain/Isense) stays within 10% in the temperature range between 25°C and 175°C, which is desirable for the current sensor of high power devices. Furthermore, the main current shut-off operation at an over-current detected using the current sensor has been demonstrated successfully.

Experimental demonstration of the active trench layout tuned 1200V CSTBT™ for lower dV/dt surge and turn-on switching loss

Optimization of a cell structure affecting gate capacitance must have an important role to upgrade usability of IGBT at high frequency operation. In this paper, we report an experimental study on the IGBT cell structures with various arrangements of active trenches connected to gate. Utilizing the advanced active trench layout with well-balanced capacitance realized to lower dV/dt surge and turn-on switching loss.

SiC-MOSFET Structure Enabling Fast Turn-On and -Off Switching

High speed switching is desired to reduce switching losses of SiC-MOSFETs. In order to realize SiC-MOSFETs capable of high speed switching, we numerically evaluated the electric field induced in SiC-MOSFETs during switching using an equivalent circuit model. Based on the evaluation, we designed a SiC-MOSFET, which successfully demonstrated high speed switching with a dV/dt of over 70 V/ns.

Low-loss rectifier by self-driven MOSFET with gate drive voltage control circuit

The low-loss self-driven rectifier we developed requires no external power supply and uses a novel CMOS control circuit that generates the power MOSFET drive signal by boosting the intrinsic body diode voltage drop. The rectifier significantly improved conduction loss — a 47% decrease from intrinsic-body-diode-based conduction loss — during half-wave rectification. It can replace with a common diode for a rectifier.

High Performance 0.2 µm Dual Gate Complementary MOS Technologies by Suppression of Transient-Enhanced-Diffusion using Rapid Thermal Annealing

Rapid thermal annealing (RTA) before the low temperature process is introduced in the 0.2 µm dual gate complementary metal oxide semiconductor (CMOS) process and its effect has been systematically investigated. Channel profiles of boron and phosphorus remain steep by the additional RTA process before gate oxidation, as seen by using secondary ion mass spectrometry and a simulation with the point defect based diffusion model. The most effective temperature to suppress transient-enhanced-diffusion (TED) is 900–1000°C, which can be remarkably suppressed by a 30 s treatment in the case of 900°C RTA. A steep channel profile decreases the threshold voltage and increases the transconductance. Shallow source/drain extension profiles of BF2 and phosphorus can be fabricated by an additional RTA process before sidewall spacer film deposition, which can improve the threshold voltage lowering. Consequently, a high current drivability of a 0.2 µm CMOS has been achieved by the suppression of TED using two additional RTA processes.

Observation of two in-plane epitaxial states in (001) Bi2Sr2CaCu2Ox films formed on (001) MgO

Abstract X-ray and ICP-MS characterizations are performed in c -axis oriented Bi 2 Sr 2 CaCu 2 O x (2212) films on (001) MgO single-crystal substrates. The chemical composition adjustment enables us to realize two distinctly different in-plane epitaxial states, namely 2212 [100] ‖ MgO [100] or 2212 [100] ‖ MgO [110].

Experimental study on isolation edge effects in the short channel characteristics of metal oxide semiconductor field effect transistors (MOSFETs)

Abstract We investigate experimentally the isolation edge shape effects on the short channel characteristics, i.e. the gate length dependence, of metal oxide semiconductor field effect transistors (MOSFETs) for various isolation structures, as compared with a reference MOSFET without influence of the isolation edges. For shallow trench isolation (STI), the effect, which is enhanced for gate lengths around the onset of the short channel effect and causes the threshold voltage ( V th ) to shift to the lower voltage side than that by the short channel effect, is more prominent for the trench edge with the deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e. the bird’s beak), the effect, which is also enhanced around the appearance point of the short channel effect, causes the V th values to go in the opposite direction to the case of STI. These results indicate that the isolation edge effect depends on the gate length and can be decribed in terms of the surface potential at the isolation edge being modulated by the mixing between the short channel and the isolation edge effect.