Kazuyoshi Asai

GaAs LSI-directed MESFET's with self-aligned implantation for n + -layer technology (SAINT)

Self-aligned implantation for n+-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFETs to be used in LSIs. This technology has made it possible to arbitrarily control the spacing between the n+-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FETs with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FETs without the n+-layer. Thermal emission for carriers from the source n+-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FETs is definitely smaller than that for [011] gate FETs. The threshold-voltage standard deviations for [011] gate FETs with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.

Reactively sputtered WSiN film suppresses As and Ga outdiffusion

This paper evaluates reactively sputtered WSiN films as an annealing cap for GaAs substrate. WSiN film successfully suppresses As and Ga outdiffusion. The WSiN/SiO2 /SiN/substrate multilayer annealing cap reconfirms this. As and Ga accumulate in the WSiN/SiO2 interface after annealing at 800 °C for 20 min. The accumulated As peak concentration is estimated to be 1019 atoms/cm3 . X‐ray diffraction shows WSiN film remains in an amorphous phase, exhibiting no recrystallized grain boundary. Film stress only changes by one‐half before and after annealing. These characteristics are very different from other refractory metals such as WN and WSi which change from amorphous to crystalline phase after annealing. It is therefore concluded that reactively sputtered WSiN films prevent As and Ga outdiffusion and form a good annealing cap for GaAs.

Electron-beam lithography in n + self-aligned GaAs MESFET fabrication

An electron-beam direct-writing technology for the fabrication of short-channel n+sef-aligned (SAINT) GaAs MESFETs is discussed. A four-level multiresist which includes a thin Mo layer is developed to avoid charging in the semi-insulating GaAs substrate. The alleviation of short channel effects is experimentally demonstrated by reducing the n+layer depth. A ring oscillator with a 0.3-µm-long gate SAINT FET shows a minimum propagation delay time of 16.7 ps with an associated power dissipation of 7.3 mW, which is one of the fastest among room-temperature semiconductor devices.

High microwave and ultra-low noise performance of fully ion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 mu m demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K/sub f/ factor of 1.4 estimated by Fukuis noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high. >

Effects of neutral buried p-layer on high-frequency performance of GaAs MESFETs

Fully ion-implanted n/sup +/ self-aligned GaAs MESFETs with Au/WSiN refractory metal gates have been fabricated by adopting neutral buried p-layers formed by 50-keV Be-implantation. S-parameter measurements and equivalent circuit fittings are discussed. When the Be dose is increased from 2*10/sup 12/ cm/sup -2/ to 4*10/sup 12/ cm/sup -2/, the maximum value of the cutoff frequency with a 0.2- mu m gate falls off from 108 to 78 GHz. This is because a neutral buried player makes the intrinsic gate-source capacitance increase markedly, while its influence on gate-drain capacitance and gate-source fringing capacitance is negligible. The maximum oscillation frequency recovers, however, due primarily to the drain conductance suppression by the higher-concentration buried p-layer. An equivalent value of over 130 GHz has been obtained for both 0.2- mu m-gate GaAs MESFETs. >

N+ Self-Aligned MESFET for GaAs LSIs

The SAINT (Self-Aligned Implantation for N+-layer Technology) procers can embed n+- layers with very low resistance at a controlled distance from Schottky gate. It has been experimentally ascertained that the SAINT has feasibility for GaAs LSIs with advantages of gain, speed, uniformity and stability. An optimum n+-gate spacing in view of resistance-capacitance trade-off is found by combination of experiments and two-dimensional simulation. Guiding principles for the submicron gate are quantitatively discussed with results of the simulation.

A Large Barrier Height Schottky Contact between Amorphous Si-Ge-B and GaAs

Electrical properties of contacts between amorphous Si–Ge–B and GaAs are studied. A Schottky contact with a barrier height as large as 0.99 V has been realized. The barrier height can be varied by changing the composition of the amorphous films. Amorphous Si–Ge–B is applied to GaAs FETs as gate electrodes. A large saturated drain current of 900 µA/10 µm gate width has been realized. This value is 1.88 times as large as conventional normally-off GaAs MESFETs.

A high density GaAs static RAM process using MASFET

A newly-developed GaAs static RAM process is described. A large transconductance (gm) of 260 mS/mm has been obtained for enhancement-mode FETs. The large transconductance is accomplished with both buried p-layer SAINT (BP-SAINT) and shallow 30 keV n-layer ion implantation applied to Metallic Amorphous Silicon gate (MAS) FET. A novel static RAM cell layout drastically reduces its cell area to 455 µm2. To realize such a compact cell, tri-level interconnections and electron beam delineated 0.8 µm × 1.3 µm via holes directly on gates and ohmic metals have been developed.

Fabrication technology for an 80-ps normally-off GaAs MESFET logic

Fabrication technology of a high-speed normally-off GaAs MESFET logic has been described. Anodic Oxidation process is applied to control epitaxial layer thickness precisely. A SiO2cap during alloying ohmic metal is used to prevent the ohmic layer surface from becoming uneven. A sloped mesa structure edge is used to avoid disconnection of metal interconnection. Electron-beam direct writing is employed to define a submicrometer gate. Applying these technologies, high-speed and small switching energy have been accomplished. The minimum delay timd and the associated switching energy were 77 ps and 75 fJ at room temperature and 51 ps and 97 fJ at 77 K.

1/4 miniaturized passive elements for GaAs MMICs

Novel miniature structures for passive elements-inductors and capacitors-are proposed to reduce the area they consume in GaAs MMICs. The miniaturized inductors are fabricated out of thick metal micro-wire, 10 mu m thick, 6 mu m wide, and with 2 mu m spacing. The miniaturized capacitors are constructed as a corrugated structure with an insulator layer sandwiched between electrodes on a SI GaAs substrate with 3- mu m-deep taper holes, in a checkerboard pattern. Both elements are fabricated employing very simple technology as a result of their monolayer structures. Adopting the proposed structures, the elements have been shrunk to 1/4 the size of conventional elements.<<ETX>>