Kee Sup Kim

Robust system design with built-in soft-error resilience

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A systems susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

X-compact: an efficient response compaction technique for test cost reduction

We present a technique for compacting test response data using combinational logic circuits. Our compaction technique enables up to an exponential reduction in the number of pins required to collect test response from a chip. The combinational circuits require negligible area, do not add any extra delay during normal operation, guarantee detection of defective chips even in the presence of sources of unknown logic values (often referred to as Xs) and preserve diagnosis capabilities for all practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test data volume, test-I/O pins and tester channels, and also to improve test quality.

X-compact: an efficient response compaction technique

X-Compact is an X-tolerant test response compaction technique. It enables up to exponential reduction in the test response data volume and the number of pins required to collect test response from a chip. The compaction hardware requires negligible area, does not add any extra delay during normal operation, guarantees detection of defective chips even in the presence of unknown logic values (often referred to as Xs), and preserves diagnosis capabilities for most practical scenarios. The technique has minimum impact on current design and test flows, and can be used to reduce test time, test-data volume, test-input/output pins and tester channels, and also to improve test quality.

Sequential Element Design With Built-In Soft Error Resilience

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements

Combinational Logic Soft Error Correction

We present two techniques for correcting radiation-induced soft errors in combinational logic - error correction using duplication, and error correction using time-shifted outputs. Simulation results show that both techniques reduce combinational logic soft error rate by more than an order of magnitude. Soft errors affecting sequential elements (latches and flip-flops) at combinational logic outputs are automatically corrected using these techniques

Delay defect characteristics and testing strategies

Several factors influence production delay testing and corresponding DFT techniques: defect sources, design styles. ability to monitor process characteristics, test generation time. available test time, and tester memory. We present an overview of delay defect characteristics and the impact of delay defects on IC quality. We also discuss practical delay-testing strategy in terms of test pattern generation, test application speed, DFT, and test cost.

Built-In Soft Error Resilience for Robust System Design

Built-in soft error resilience (BISER) is an architecture-aware circuit design technique for correcting soft errors in latches, flip-flops and combinational logic. BISER enables more than an order of magnitude reduction in chip-level soft error rate with minimal area impact, 6-10% chip-level power impact, and 1-5% performance impact (depending on whether combinational logic error correction is implemented or not). In comparison, several traditional error-detection techniques introduce 40-100% power, performance and area penalties, and require significant efforts for designing and validating corresponding recovery mechanisms. In addition, BISER enables system design with configurable soft error protection features. Such features are extremely important for future designs targeting applications with a wide range of power, performance and reliability constraints. Design trade-offs associated with BISER and other existing soft error protection techniques are also analyzed.

Logic soft errors: a major barrier to robust platform design

Radiation induced soft errors in flip-flops, latches and combinational logic circuits, also called logic soft errors, pose a major challenge in the design of robust platforms for enterprise computing and networking applications. Associated power and performance overheads are major barriers to the adoption of classical fault-tolerance techniques to protect such systems from soft errors. Design-for-functional-test and debug resources can be reused for built-in soft error resilience during normal system operation resulting in more than an order of magnitude reduction in the undetected soft error rate. This design technique has negligible area and speed penalties, and the chip-level power penalty is significantly smaller compared to classical fault-tolerance techniques

XMAX: X-tolerant architecture for MAXimal test compression

XMAX is a novel test data compression architecture capable of achieving almost exponential reduction in scan test data volume and test time while allowing use of commercial automatic test pattern generation (ATPG) tools. It tolerates presence of sources of unknown logic values (also referred to as Xs) without compromising test quality and diagnosis capability for most practical purposes. The XMAX architecture has been implemented in several industrial designs.

Design for Resilience to Soft Errors and Variations

This paper presents adaptive variation-and-error-resilient agent (AVERA), an approach to address the challenge of designing reliable systems in the presence of soft errors and variations. AVERA extends our previous built-in soft error resilience (BISER) approach by adding additional capabilities to support process variation diagnosis, degradation detection, and system adaptation, besides soft error correction. We also discuss open challenges for building variation-and-error-resilient systems.