Kehan Zhu

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Nanoscale resistive memory devices are expected to fuel dense integration of electronic synapses for large-scale neuromorphic systems. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in situ learning and computing while driving a large number of resistive synapses is desired. This brief presents a novel leaky integrate-and-fire neuron design that implements the dual-mode operation of current integration and synaptic drive, with a single operational amplifier (opamp) and enables in situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18-μm CMOS technology. Measurements show neurons ability to drive a thousand resistive synapses and demonstrate in situ associative learning. The neuron circuit occupies a small area of 0.01 mm2 and has an energy efficiency value of 9.3 pJ/spike/synapse.

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.

Compact Verilog-A Modeling of Silicon Traveling-Wave Modulator for Hybrid CMOS Photonic Circuit Design

A compact Verilog-A model of silicon-based junction traveling-waveMach-Zehnder modulator (MZM) is developed for hybrid CMOS and photonic system-level simulation in Cadence environment. Critical device functions such as the voltage dependent change of refractive index, small-signal RLGC parameters for the MZM arms are extracted from the photonic device characterization from OpSIS foundry. Thermo-optical coefficient is also considered in the model. Simulation results including electro-optic S21 is characterized for the phase modulators bandwidth. Also, transient MZM operation with non-return to zero (NRZ) data transmission at 10 Gb/s and 20 Gb/s rates are demonstrated.

A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy-inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigurable architecture with a single opamp, the described neuron accommodates a large number of memristor synapses, and enables online spike timing dependent plasticity (STDP) learning with optimized power consumption. Simulation results of an 180nm CMOS design showed 97% power efficiency metric when realizing STDP learning in 10,000 memristor synapses with a nominal 1MΩ memristance, and only 13μA current consumption when integrating input spikes. Therefore, the described CMOS neuron contributes a generalized building block for large-scale brain-inspired neuromorphic systems.

Design Considerations for Traveling-Wave Modulator-Based CMOS Photonic Transmitters

Systematic design and simulation methodology for hybrid optical transmitters that combine CMOS circuits in a 130-nm process and a traveling-wave Mach-Zehnder modulator (TWMZM) in a 130-nm silicon-on-insulator CMOS process is presented. A compact Verilog-A model for the TWMZM is adopted for the electrooptical simulation. A bond wire model using a high-frequency solver is included for accurate package simulation. The transmitter post-layout simulation result exhibits 5.48-dB extinction ratio, 9.6-ps peak-to-peak jitter, and the best power efficiency of 5.81 pJ/bit when operating up to 12.5-Gb/s non-return-to-zero data. A pulse-amplitude modulation four-level transmitter with a detailed linearity design procedure is presented, which has horizontal and vertical eye openings of 49 ps and 203 μW when operating at 25 Gb/s, and has power efficiency is 5.09 pJ/bit.

Design Analysis of a 12.5 GHz PLL in 130 Nm SiGe BiCMOS Process

A systematic design method is applied to study and analyze the loop stability and phase noise of a type-II 3rd-order charge pump PLL. The designed PLL outputs at 12.5 GHz, which is intended to provide a clock for a silicon photonic transmitter prototype. The charge pump current and loop filter resistor are made tunable to cover process and temperature variations. The PLL is designed in a 130 nm SiGe BiCMOS process. The rms jitter of the studied PLL output is about 5 ps with a 97.7 MHz reference clock with 4.9 ps rms jitter from a 0.05 to 12.5 GHz signal generator. The total power consumption of the PLL is less than 175 mW from a 2.5 V power supply.

Systematic design of 10-bit 50MS/s pipelined ADC

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter

Low-cost optical interconnects are playing an important role in sustaining the exponential growth in data center demand and to support the future internet-of-things cloud infrastructure. These chip-scale optical transceiver systems are integrated using two-chip bonding solution of CMOS electronic die with a silicon photonic die. In this work, modeling of the critical bond-wire is performed with electromagnetic field solver to optimize the integration of a silicon photonic transmitter, which is composed of a current mode driver in a 130 nm CMOS process and a traveling-wave Mach-Zehnder modulator (MZM) in a SOI photonic process, respectively. It is shown that the bond-wire can be optimized for bandwidth extension using series peaking with the open-drain current mode driver. However, it degrades the bandwidth when using a voltage mode driver. A compact, experimentally verified, Verilog-A model for the MZM is adopted for the electro-optical simulation. Further, it is demonstrated that a minimum length of the bond-wire and a minimum spacing between two signal bond-wires are required to ensure the bandwidth of the system with hybrid simulation. A MZM device chip-on-board wire bonded on PCB is demonstrated operating up to 12.5 Gb/s.

A comprehensive design approach for a MZM based PAM-4 silicon photonic transmitter

A 4-level pulse amplitude modulation (PAM-4) silicon photonic transmitter targeting operation at 25 Gb/s is designed using an electrical-photonic co-design methodology. The prototype consists of an electrical circuit and a photonics circuit, which were designed in 130 nm IBM SiGe BiCMOS process and 130nm IME SOI CMOS process, respectively. Then the two parts will be interfaced via side-by-side wire bonding. The electrical die mainly includes a 12.5 GHz PLL, a full-rate 4-channel uncorrelated 27 - 1 pseudo-random binary sequence (PRBS) generator and CML drivers. The photonics die is a 2-segment Mach-Zehnder modulator (MZM) silicon photonics device with thermal tuning feature for PAM-4. Verilog-A model for the MZM entails the system simulation for optical devices together with electrical circuitry using custom IC design tools. A full-rate 4-channel uncorrelated PRBS design using transition matrix method is detailed, in which any two of the 4-channels can be used for providing random binary sequence to drive the two segments of the MZM to generate the PAM-4 signal.

Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects

A 10-Gb/s integrated limiting receiver for silicon photonics interconnects is proposed with detailed system level and circuit level design and analysis. Silicon photonics devices fabricated in silicon-on-insulator (SOI) can be seamlessly integrated with standard CMOS process, which allows compact system integration and significantly lower power dissipation. By taking the advantages of low parasitic capacitance of the on-chip Germanium (Ge) detector and adopting bandwidth extension techniques, a total bandwidth of 7.2 GHz with 87 mW power consumption is obtained in a 0.13-μm CMOS process. The final differential output signal has a peak-to-peak swing of about 1.2 V and a peak-to-peak jitter of 14.3 ps and 9.8 ps for 10-Gb/s 27 - 1 PRBS data with an average received optical power of -17 dBm and 0 dBm, respectively.