Sakkarapani Balagopal

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Nanoscale resistive memory devices are expected to fuel dense integration of electronic synapses for large-scale neuromorphic systems. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in situ learning and computing while driving a large number of resistive synapses is desired. This brief presents a novel leaky integrate-and-fire neuron design that implements the dual-mode operation of current integration and synaptic drive, with a single operational amplifier (opamp) and enables in situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18-μm CMOS technology. Measurements show neurons ability to drive a thousand resistive synapses and demonstrate in situ associative learning. The neuron circuit occupies a small area of 0.01 mm2 and has an energy efficiency value of 9.3 pJ/spike/synapse.

Systematic design of multi-bit continuous-time delta-sigma modulators using two-step quantizer

A 500 MS/s, wideband 4th order continuous-time delta sigma modulator (CT-ΣΔM) using a two-step 5-bit quantizer, consisting of only 10 comparators, is proposed and presented using 0.18µm CMOS technology. A proposed modulator takes advantage of the high resolution two step quantization technique and an excess loop compensation of more than one cycle to achieve a low-power, high dynamic range with a wide conversion bandwidth. A robust systematic design method is used to determine the loop filter coefficients by considering the non-ideal opamps effects including the finite gain and the presence of multiple internal poles and zeros. The proposed CT-ΣΔM achieves a dynamic range of 75.83 dB, peak SNR of 75.1 dB with 25 MHz bandwidth (OSR = 10) while consuming only 27.5 mW from the 1.8 V supply. The relevant design trade offs have been investigated and presented with simulation results.

Efficient design and synthesis of decimation filters for wideband delta-sigma ADCs

A design methodology for synthesizing power-optimized decimation filters for wideband Delta Sigma (ΔΣ) analog-to-digital converters (ADCs) for next-generation wireless standards is presented. The decimation filter is designed to filter the out-of-band quantization noise from a fifth-order continuous-time ΔΣ modulator, with 20 MHz signal bandwidth and 14-bits resolution. The modulator employs an oversampling ratio (OSR) of 16 with a clock rate of 640 MHz. Retiming, pipelining, Canonical Signed Digits (CSD) encoding has been utilized along with an optimized halfband filter to realize the power savings in the overall decimation filter. A process flow to rapidly design the optimized filters in MATLAB, generate the hardware description language (HDL) code and then automatically synthesize the design using standard cells has been presented. The decimation filter is implemented using standard cells in a 45nm CMOS technology occupies a layout area of 0.12mm2 and consumes 8 mW power from the 1.1V supply.

Systematic design of three-stage op-amps using split-length compensation

Over the past decade CMOS technology has been continuously scaling which has resulted in sustained improvement in transistor speeds. However, the transistor threshold voltages do not decrease at the same rate as the supply voltage (VDD). Besides, the open-loop gain available from the transistors is diminishing. This trend renders the traditional techniques, like cascoding and gain boosting, less useful for achieving high DC gain in nano-scale CMOS processes. Thus, horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low-VDD processes. This paper presents a design procedure for op-amp design using split-length compensation. A reversed-nested split-length compensated (RSLC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RSLC topology is then extended to the design of three-stage fully-differential op-amps.

Systematic design of 10-bit 50MS/s pipelined ADC

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

Multi-bit continuous-time delta-sigma modulator for audio application

The design considerations for low-power continuous time (CT) delta-sigma (ΔΣ) modulators is studied and circuit design details for a 13.5 bit modulator are given. The converter has been designed in a 0.5 um C5FN AMI CMOS technology and achieves a maximum signal-to-noise ratio (SNR) of 85 dB in a 48 kHz bandwidth and dissipates 5.4 mW from a 5 V supply when clocked at 6.144 MHz. It features a third-order active-RC loop filter, a 4-bit flash quantizer along with a Data Weighted averaging (DWA). The loop filter architecture and its coefficients have been targeted for the minimum power dissipation. The DWA also has been implemented by standard cell based synthesis to further optimize power. The figure of merit (FoM) of the CT-ΔΣ modulator is 3.71 pJ/bit. The fabricated chip of the modulator occupies an area of 4.5 mm2.

Design of a 10-Gb/s integrated limiting receiver for silicon photonics interconnects

A 10-Gb/s integrated limiting receiver for silicon photonics interconnects is proposed with detailed system level and circuit level design and analysis. Silicon photonics devices fabricated in silicon-on-insulator (SOI) can be seamlessly integrated with standard CMOS process, which allows compact system integration and significantly lower power dissipation. By taking the advantages of low parasitic capacitance of the on-chip Germanium (Ge) detector and adopting bandwidth extension techniques, a total bandwidth of 7.2 GHz with 87 mW power consumption is obtained in a 0.13-μm CMOS process. The final differential output signal has a peak-to-peak swing of about 1.2 V and a peak-to-peak jitter of 14.3 ps and 9.8 ps for 10-Gb/s 27 - 1 PRBS data with an average received optical power of -17 dBm and 0 dBm, respectively.

Design of wideband continuous-time ΔΣ ADCs using two-step quantizers

Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-ΔΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-ΔΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.

Systematic synthesis of cascaded continuous-time ΔΣ ADCs for wideband data conversion

Continuous-time delta sigma (CT-ΔΣ ) ADCs are gaining wider adoption in data conversion systems primarily aided by their robustness to mismatch in nano-scale CMOS technologies and inherent anti-alias filtering. In past, several techniques have been employed to achieve wider conversion bandwidths by either scaling the designs to a lower technology node or by adopting architectures with lower oversampling ratios (OSR). Cascaded, or MASH, CT-ΔΣ ADCs have been explored to achieve conversion bandwidths by cascading lower order ΔΣ loops followed by a digital coarse quantization noise canceling filter (NCF). Another technique which has recently been explored is to increase the quantizer sampling rate, in a given technology node, by absorbing excess loop-delay (ELD) greater than one clock cycle (Ts) in the loop. However, these techniques individually cannot sufficiently meet the ever increasing bandwidth demand for the broadband wireless applications. Further, the ELD > Ts designs require an extra modulator order to achieve the same noise-shaping performance as the low-speed ELD <; 0.5 Ts prototype, necessitating high-order CT-ΔΣ loops. As a step towards combing the two techniques, we propose a systematic design method to synthesize 3-2 MASH CT-ΔΣ modulators to achieve higher conversion bandwidths, BW ≥ 40MHz in a 130-nm CMOS technology.

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-ΔΣ ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s Continuous-time Delta-Sigma modulator (CT-ΔΣM) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB signal-to-noise is reported in a 0.13μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT-ΔΣ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT-ΔΣM has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.