Vishal Saxena

Design and fabrication of a MEMS capacitive chemical sensor system

This paper describes the development of a MEMS sensor system to detect volatile compounds. The sensor consists of a MEMS capacitive sensor element monolithically integrated with a sensing circuit. The sensor element is a parallel plate capacitor using a chemically sensitive polymer as the dielectric. In presence of the target analyte, the polymer swells and changes the capacitance of the sensor element. This change in capacitance is sensed and converted to a digital bit stream by a delta-sigma sensing circuit. This paper provides an overview of the design of the sensor element, the sensing circuit and the process integration for their fabrication on a single die

A CMOS Spiking Neuron for Brain-Inspired Neural Networks With Resistive Synapses and In Situ Learning

Nanoscale resistive memory devices are expected to fuel dense integration of electronic synapses for large-scale neuromorphic systems. To realize such a brain-inspired computing chip, a compact CMOS spiking neuron that performs in situ learning and computing while driving a large number of resistive synapses is desired. This brief presents a novel leaky integrate-and-fire neuron design that implements the dual-mode operation of current integration and synaptic drive, with a single operational amplifier (opamp) and enables in situ learning with crossbar resistive synapses. The proposed design was implemented in a 0.18-μm CMOS technology. Measurements show neurons ability to drive a thousand resistive synapses and demonstrate in situ associative learning. The neuron circuit occupies a small area of 0.01 mm2 and has an energy efficiency value of 9.3 pJ/spike/synapse.

Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.

High speed digital input buffer circuits

This paper illustrates design, fabrication and testing of novel differential high-speed digital input buffers. The delay of the proposed input buffers are nearly independent of power supply voltage and input signal amplitudes. The pulse shape of the output signal is highly symmetric which mitigates skew related errors

Indirect feedback compensation of CMOS op-amps

This paper presents the design of CMOS op-amps using indirect feedback compensation technique. The indirect feedback compensation results in much faster and low power op-amps, significant reduction in the layout size and better power supply noise rejection

W-2W Current Steering DAC for Programming Phase Change Memory

This paper presents the design and experimental results of W-2W current mirror binary-weighted current steering digital-to-analog converter (DAC) and its application for programming phase change memory (PCM). This new approach significantly reduces the layout area of current-mode DACs by the virtue of its compact size. The proposed DAC can replace the write driver circuits in phase change memories. Both 6-bit and 12-bit DACs have been fabricated in 0.5 mum CMOS technology. The layout size of the 12-bit and the 6-bit DACs is 0.09 mm 2 and 0.04 mm 2 respectively. Experimental results are presented and the limitations are discussed.

Indirect compensation techniques for three-stage fully-differential op-amps

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by cascoding become less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses indirect compensation techniques for op-amps using split-length devices. A reversed-nested indirect compensated (RNIC) topology, employing double pole-zero cancellation, is illustrated for the design of three-stage op-amps. The RNIC topology is then extended to the design of three-stage fully-differential op-amps. Novel three-stage fully-differential gain-stage cascade structures are presented with efficient common mode feedback (CMFB) stabilization. Simulation results are presented for the designed RNIC fully-differential three-stage op-amps. The fully-differential three-stage op-amps, designed in 0.5 µm CMOS, typically exhibit 18 MHz unity-gain frequency, 82 dB open-loop DC gain, nearly 300 ns transient settling and 72° phase-margin for a 500 pF load.

Indirect compensation techniques for three-stage CMOS op-amps

As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100ns transient settling and 72° phase-margin for 500pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area.

Compact Verilog-A Modeling of Silicon Traveling-Wave Modulator for Hybrid CMOS Photonic Circuit Design

A compact Verilog-A model of silicon-based junction traveling-waveMach-Zehnder modulator (MZM) is developed for hybrid CMOS and photonic system-level simulation in Cadence environment. Critical device functions such as the voltage dependent change of refractive index, small-signal RLGC parameters for the MZM arms are extracted from the photonic device characterization from OpSIS foundry. Thermo-optical coefficient is also considered in the model. Simulation results including electro-optic S21 is characterized for the phase modulators bandwidth. Also, transient MZM operation with non-return to zero (NRZ) data transmission at 10 Gb/s and 20 Gb/s rates are demonstrated.

A CMOS spiking neuron for dense memristor-synapse connectivity for brain-inspired computing

Neuromorphic systems that densely integrate CMOS spiking neurons and nano-scale memristor synapses open a new avenue of brain-inspired computing. Existing silicon neurons have molded neural biophysical dynamics but are incompatible with memristor synapses, or used extra training circuitry thus eliminating much of the density advantages gained by using memristors, or were energy-inefficient. Here we describe a novel CMOS spiking leaky integrate-and-fire neuron circuit. Building on a reconfigurable architecture with a single opamp, the described neuron accommodates a large number of memristor synapses, and enables online spike timing dependent plasticity (STDP) learning with optimized power consumption. Simulation results of an 180nm CMOS design showed 97% power efficiency metric when realizing STDP learning in 10,000 memristor synapses with a nominal 1MΩ memristance, and only 13μA current consumption when integrating input spikes. Therefore, the described CMOS neuron contributes a generalized building block for large-scale brain-inspired neuromorphic systems.