Keiji Emoto

Nanoimprint system development and status for high-volume semiconductor manufacturing

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field. The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve.

Defectivity and particle reduction for mask life extension, and imprint mask replication for high-volume semiconductor manufacturing

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm. Hard particles on a wafer or mask create the possibility of creating a permanent defect on the mask that can impact device yield and mask life. By using material methods to reduce particle shedding and by introducing an air curtain system, test stand results demonstrate the potential for extending mask life to better than 1000 wafers. Additionally, a new replication tool, the FPA-1100 NR2 is introduced. Mask chuck flatness simulation results were also performed and demonstrate that residual image placement errors can be reduced to as little as 1nm.

Improved particle control for high volume semiconductor manufacturing for nanoimprint lithography

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. To meet the CoO requirements, mask life must meet or exceed 1000 wafers. If, we make the conservative assumption that every particles causes damage to the mask pattern, the number of particle adders must be less than 0.001 pieces per wafer pass in the NIL tool. Therefore, aggressive strategies are needed to reduce particles in the tool. In this paper, we will report on the techniques required to meet this condition and will describe how the particle reduction techniques can be extended to our FPA-1200NZ2C system.