Keiki Watanabe

43 Gb/s full-rate-clock 16:1 multiplexer and 1:16 demultiplexer with SFI-5 interface in SiGe BiCMOS technology

Fabricated in 0.18 /spl mu/m SiGe BiCMOS, 16:1 MUX and 1:16 DMUX MCMs equipped with an SFI-5 interface operate at 43 Gb/s. The on-chip CDR with external VCO recovers a full-rate clock with 2.5/spl deg/ RMS jitter from 2/sup 31/-1 PRBS. The SFI-5 bus also operates error-free at 2.7 Gb/s, and tolerates a /spl plusmn/6.6 Ul static skew.

A low-jitter 16:1 MUX and a high-sensitivity 1:16 DEMUX with integrated 39.8 to 43GHz VCO for OC-768 communication systems

A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.

A wireless biosensing chip for DNA detection

A wireless sensing chip for biological assay is fully operational in a sample solution. The IC monolithically integrates a biological sensor, an RF communication circuit, and a coupling coil on a 2.5/spl times/2.5 mm/sup 2/ chip in 0.35 /spl mu/m CMOS technology. Detection of single nucleotide polymorphism (SNP) in DNA is successfully carried out by the chip.

A single-chip 10 Gb/s transceiver LSI using SiGe SOI/BiCMOS

A fully-integrated single-chip SiGe SOI/BiCMOS transceiver LSI for 10 Gb/s applications combines 4b FIFO, 10 GHz PLL, 16:1 MUX, 10 Gb/s input data decision circuit, clock and data-recovery circuit, 1:16 DeMUX, data loop back function, and self-testing using 2/sup 23/-1 PRBS generator. The die is 5.6/spl times/5.3 mm/sup 2/ and consumes 2.6 W from 3.3/2.5 V.

Fully monolithically integrated 40-Gbit/s transmitter and receiver

40-Gbit/s ETDM transmitter and receiver, both with a 10-Gbit/s interface have been developed. All ICs used in the transmitter and receiver are integrated monolithically by using InP HBTs and SiGe HBTs.

A fully integrated 39.8-/43-GHz VCO - featuring wide tuning range and low temperature drift - for single-chip MUX/DEMUX LSIs

A fully integrated 39.8-/43-GHz switchable VCO was developed for practical single-chip MUX/DEMUX LSIs in 0.18 /spl mu/m SiGe BiCMOS technology . The VCO provides a clock signal for data rates of 39.8 and 43.0 Gbps. The VCO has a novel configuration of a half-frequency VCO and a frequency doubler to realize a 7 GHz tuning range, for tolerating process deviation and supporting dual mode operation. A new temperature compensation technique resulted in a 0.6% temperature fluctuation of oscillation frequency. Measured phase noise at a 1 MHz offset frequency was -85.0 dBc/Hz. Data transmission experiments between the MUX and DEMUX confirmed that this phase noise is allowable for use in 40-Gbps class network systems.

A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication

A 21-channel 8 Gb/s transceiver is implemented in a 90 nm CMOS technology. 168 Gb/s uncoded data transmission with 3.6 ns latency is achieved with 4-tap FFE, receiver equalization, jitter tolerant CDR and low jitter PLL. Measured bathtub plots for 80 cm FR-4 backplane indicate BER<10-15 with 0.11 UI phase margin at the nominal power consumption of 160 mW/ch.