Nobuhiro Shiramizu
Hitachi
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Featured researches published by Nobuhiro Shiramizu.
radio frequency integrated circuits symposium | 2005
Nobuhiro Shiramizu; Tom Masuda; Masamichi Tanabe; Katsuyoshi Washio
We have developed a SiGe HBT low-noise amplifier (LNA) for ultra-wideband (UWB) systems. We reduced the noise figure (NF) over the frequency range from 3.1 to 10.6 GHz (the FCC-specified UWB range) by using a novel LNA structure with an inductor-terminated, common-base input stage in front of a resistive-feedback amplifier. The circuit topology simultaneously enables increased gain for the input stage and wideband noise matching. On-chip measurement using microwave probes has shown that the LNA - fabricated using commercially available 0.25- /spl mu/m SOI SiGe BiCMOS technology - provides a wide 3-dB bandwidth of 14.5 GHz, an S21 of 22 dB, and a low noise figure ranging from 2.7 dB to 3.9 dB, along with low power consumption of 13.2 mW. Deviation of the S21 group delay is kept within 25 ps to ensure faithful signal amplification. The LNA occupies a chip area of 0.49 mm/sup 2/.
international microwave symposium | 2001
Toru Masuda; K. Ohhata; Nobuhiro Shiramizu; E. Ohue; K. Oda; R. Hayami; H. Shimamoto; Masao Kondo; T. Harada; Katsuyoshi Washio
A 4:1 multiplexer and a 1:4 demultiplexer IC module were developed by using 0.2 /spl mu/m self-aligned selective-epitaxial-growth SiGe HBTs. For the data retiming, the multiplexer and the demultiplexer include a frequency divider that operates at over 40 GHz. 50-Gb/s operation for the multiplexer and 48-Gb/s operation for the demultiplexer were observed by measurements using on-wafer probes. We concluded that these modules, which mounted the IC on a ceramic substrate with a brass block, are applicable to transmitter and receiver functions of a 40-Gb/s optical transmission system.
international solid-state circuits conference | 2003
Akio Koyama; T. Harada; Hiroki Yamashita; R. Takeyari; Nobuhiro Shiramizu; Kyosuke Ishikawa; Masahiro Ito; S. Suzuki; T. Yamashita; S. Yabuki; H. Ando; Tatsuhiro Aida; Keiki Watanabe; K. Ohhata; S. Takeuchi; H. Chiba; Atsushi Ito; Hiroyuki Yoshioka; A. Kubota; T. Takahashi; H. Nii
Fabricated in 0.18 /spl mu/m SiGe BiCMOS, 16:1 MUX and 1:16 DMUX MCMs equipped with an SFI-5 interface operate at 43 Gb/s. The on-chip CDR with external VCO recovers a full-rate clock with 2.5/spl deg/ RMS jitter from 2/sup 31/-1 PRBS. The SFI-5 bus also operates error-free at 2.7 Gb/s, and tolerates a /spl plusmn/6.6 Ul static skew.
international solid-state circuits conference | 2000
Toru Masuda; K. Ohhata; Fumihiko Arakawa; Nobuhiro Shiramizu; Eiji Ohue; Katsuya Oda; R. Hayami; Masamichi Tanabe; Hiromi Shimamoto; M. Kondo; Takashi Harada; Katsuyoshi Washio
A preamplifier with 45 GHz bandwidth and 50.2 dB/spl Omega/ transimpedance gain, a limiting amplifier with 32 dB gain and 49 GHz bandwidth, and a 40 Gb/s 1:4 high-sensitivity demultiplexer (HS-DEMUX) combined with a decision circuit are for use in a 40 Gb/s optical receiver. The bandwidth in the preamplifier and the maximum gain at 40 GHz in the limiting amplifier are the best reported for any semiconductor technology. The 1:4 HS-DEMUX uses bit-rotation for byte-synchronization.
international solid-state circuits conference | 2004
Keiki Watanabe; Akio Koyama; T. Harada; Tatsuhiro Aida; Atsushi Ito; Tomoo Murata; Hiroyuki Yoshioka; Masahito Sonehara; Hiroki Yamashita; Kyosuke Ishikawa; Masahiro Ito; Nobuhiro Shiramizu; Takahiro Nakamura; K. Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; H. Chiba; Tsutomu Kurihara; Mamoru Kuraishi
A fully integrated 39.8 to 43Gb/s OC-768 16:1 MUX/DEMUX chipset is implemented in a 0.18/spl mu/m BiCMOS process. Full-rate operation is realized with an on-chip VCO, and the chipset dissipates 11.6W. The measured output jitter of the packaged MUX is 630fs, and the sensitivity of DEMUX is 31 mV/sub PP/ single-ended with a BER <10/sup -12/.
international microwave symposium | 2001
K. Ohhata; Fumihiko Arakawa; Tom Masuda; Nobuhiro Shiramizu; Katsuyoshi Washio
40 Gb/s analog IC chipset, an AGC amplifier, a full-wave rectifier and a decision circuit, for optical receivers were developed using SiGe HBT technology. The high performance SiGe HBT and optimized circuit configuration make possible an AGC amplifier with a 47.8 GHz bandwidth, a full-wave rectifier, and a decision circuit with 40 Gb/s operation.
european solid-state circuits conference | 2006
Takahiro Nakamura; Toru Masuda; Nobuhiro Shiramizu; Katsuyoshi Washio; Tomomitsu Kitamura; Norio Hayashi
A novel wide-tuning-range LC-tuned voltage-controlled oscillator (LC-VCO) - featuring small VCO-gain (KVCO) fluctuation - was developed. For small KVCO fluctuation, a serial LC-resonator that consists of an inductor, a fine-tuning varactor, and a capacitor bank was added to a conventional parallel LC-resonator that uses a capacitor bank scheme. The resonator was applied to a 3.9-GHz VCO for multi-band W-CDMA RFIC fabricated with 0.25-mum Si-BiCMOS technology. The VCO exhibited KVCO fluctuation of only 21%, which is one third that of a conventional VCO, with 34% tuning range. The VCO also exhibited a low phase noise of -121 dBc/Hz at 1-MHz offset frequency and a low current consumption of 4.0 mA
topical meeting on silicon monolithic integrated circuits in rf systems | 2008
Toru Masuda; Nobuhiro Shiramizu; Takahiro Nakamura; Katsuyoshi Washio
We propose a modeling methodology to determine the optimum dimensions of slots in ground shield metal of slow-wave transmission lines. We induce a mutual inductance between a signal conductor and return ground current paths to express an equivalent inductance of the transmission line. The models accuracy is confirmed by characterization of a fabricated transmission line TEG.
asian solid state circuits conference | 2005
Toru Masuda; Takahiro Nakamura; Masamichi Tanabe; Nobuhiro Shiramizu; Shinichiro Wada; Takashi Hashimoto; Katsuyoshi Washio
24-GHz low noise amplifier (LNA) and voltage controlled oscillator (VCO) in 0.25-mum SiGe BiCMOS technology were developed to create low-cost radio frequency (RF) modules for short-range ultra-wideband radar systems. A two-stage shunt-feedback LNA that used inductive biasing had a -3-dB bandwidth of 11.4 GHz, a noise figure of 3.8 dB at 24 GHz, and a group delay deviation within 21 ps (from 10 GHz to 30 GHz). The LC-tuned differential VCO, with a high quality-factor center-tapped inductor design, oscillated at 24 GHz with phase noise of -100 dBc/Hz at 1 MHz offset. The VCO core consumed only 2 mA of current
european solid-state circuits conference | 2008
Nobuhiro Shiramizu; Toru Masuda; Takahiro Nakamura; Katsuyoshi Washio
Design techniques for a low-power mixer operating in the quasi-millimeter-wave frequency region were developed. A pseudo-stacked configuration and a pre-biasing technique, to reduce supply voltage and dynamic current consumption, respectively, were introduced. Furthermore, a gain-boosting technique, which actively utilizes a parasitic resonant caused by a transformer and parasitic capacitor, improves the power efficiency of the mixer. The proposed mixer fabricated by 0.18-mum SiGe BiCMOS technology achieves a conversion gain of 4.8 dB and NF of 10.4 dB at 1-V power supply. These performance results indicate that these design techniques are suitable for implementing low-power receivers for the quasi-millimeter-wave frequency region.