Takashi Muto

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

The amount of data traffic is increasing year by year as the number of data-rich services like cloud services and streaming services are increasing. The number of switch modules between servers should decrease to lower latency, and several servers in each rack should be connected to one switch module with cables in a data centre. Using copper cables to connect racks is attractive in terms of cost minimization. Thin cables, for example 34 AWG copper cables, make maintenance easy. The cable length should be 5-7m to connect between racks, and 34 AWG 7m cable has 48dB loss, including board trace loss, package loss and so on. So far transceivers over 25Gb/s, equalizing 35-40dB channel loss have been proposed [1-4], with which low-loss cables like 26 AWG have been required. We target a 25Gb/s transceiver equalizing over 50dB channel loss, and adopt a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer. Both improve on the minimum input sensitivity and enable data transmission through a channel with over 50dB loss.

6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers

Recently, there has been strong demand for high-resolution CMOS image sensors (large number of pixels) in the fields of security, science, and other specialized areas [1,2]. One of the major issues in realizing high-resolution image sensors is to speed up signal readout. For high-speed signal readout, it is necessary to accelerate pixel readout, AD conversion in column circuits, horizontal data output from column memories, and digital data output from the chip. Single-slope ADCs (SS-ADC) are the most common architecture in commercialized CMOS image sensors; increasing their counting clock frequency up to 2.376GHz [3] and using multiple ramp signals [4] can shorten the AD conversion period. However, the former has difficulty in maintaining the clock quality and suppressing power dissipation due to the high clock frequency, and the latter has difficulty in controlling the uniformity and the quality of the multiple ramp signals. Another significant issue is power consumption. Rise of power consumption with increase in number of columns results in non-uniformity of power supply to the column circuits due to IR drops. It may give rise to degradation of image quality such as fixed pattern noise, etc.

A 21-channel 8Gb/s transceiver macro with 3.6ns latency in 90nm CMOS for 80cm backplane communication

A 21-channel 8 Gb/s transceiver is implemented in a 90 nm CMOS technology. 168 Gb/s uncoded data transmission with 3.6 ns latency is achieved with 4-tap FFE, receiver equalization, jitter tolerant CDR and low jitter PLL. Measured bathtub plots for 80 cm FR-4 backplane indicate BER<10-15 with 0.11 UI phase margin at the nominal power consumption of 160 mW/ch.

3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.

Power, signal integrity for 25-Gbps, 40-dB compensation signal conditioner for backplane architecture

A 25-Gbps/lane 40-dB compensation signal conditioner was developed. The target architecture was a long channel backplane with two connectors that have large reflections due to impedance discontinuities. Jitters originating from the power integrity (PI) and signal integrity (SI) are critical for a bit error rate (BER) less than 1E-12 because 1 unit interval (UI) is small at high speed. A technique for frequency dependent decap was designed to reduce the PI jitter. Also, a non-linear equalization for the reflections technique was designed to reduce the SI jitter. Our test chip can achieve 2.5 ps PI and 10.0 ps SI jitter, respectively. The sum of the PI and SI jitter can be reduced to less than 0.32 UI. Finally, our test chip can achieve a BER of less than 1E-12 for a 40-dB backplane with two connector traces.