Keikichi Tamaru

A cyclic A/D converter that does not require ratio-matched components

A successive-approximation analog-to-digital (A/D) converter is roost widely used for intermediate-speed applications. The circuit uses accurately ratio-matched components as a precision reference element. Hence, the analog portion of the converter cannot be easily scaled down. To overcome this problem, several circuits whose conversion characteristics do not depend on ratio accuracy have been proposed [1,2].

A comparative study of switching activity reduction techniques for design of low-power multipliers

The design of portable battery-operated systems requires multiplication circuits of low switching activity. This paper studies multiplication algorithms, sign extension methods, adding structures, resource sharing and component schematic alternatives from the point of decreasing the total number of logic transitions in the target multiplication circuit. Experiments show, that by utilizing the signed-digit encoding scheme, modified sign extension technique, 4-2 adding compressors and swing restored transistor path logic, a twice as low switching activity can be achieved.

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load

We present a gate delay model of CMOS logic gates driving a CRC /spl pi/ load for deep sub-micron technology. Our approach is to replace series-parallel connected MOSFETs to an equivalent MOSFET and calculate the output waveform by an analytically derived formula. We present a MOSFET drain current model improved from the n-th power law MOSFET model to represent the characteristic of the equivalent inverter accurately. The accuracy of our gate delay model is evaluated in several gates under various conditions of input transition time and CRC parameters. The maximum error is less than 10.3% in the experiments. Our approach contributes to fast and accurate estimation of circuit speed under various supply voltage, which will enable us to optimize the circuit speed and power dissipation.

A practical gate resizing technique considering glitch reduction for low power design

We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. The effect of our method is verified experimentally using 8 benchmark circuits with a 0.6 /spl mu/m standard cell library. Our method reduces the power dissipation from the minimum-sized circuits further by 9.8% on average and 23.0% maximum. We also verify that our method is effective under manufacturing variation.

Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates

We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering current flowing from the input node to the output node through gate capacitances, the accuracy is improved significantly. The error of our formula for a CMOS inverter is less than 15% from circuit simulation in most cases. We also derive delay formulae considering the short-circuit current and the current flowing through gate capacitance. The error of this formula is smaller than 13% in our experiments. Since these formulae calculate the short-circuit power dissipation and the delay accurately and quickly, they can be applied to power sensible CAD tools.

A power optimization method considering glitch reduction by gate sizing

We propose a power optimization method considering glitch reduction by gate sizing. Our method reduces not only the amount of capacitive and short-circuit power consumption but also the power dissipated by glitches which has not been exploited previously. In the optimization method, we improve the accuracy of statistical glitch estimation method and a device gate sizing algorithm that utilizes perturbations for escaping a bad local solution. The effect of our method is verified experimentally using 12 benchmark circuits with a 0.5 /spl mu/m standard cell library. Gate sizing reduces the number of glitch transitions by 38.2% on average and by 63.4% maximum. This results in the reduction of total transitions by 12.8% on average. When the circuits are optimized for power without delay constraints, the power dissipation is reduced by 7.4% on average and by 15.7% maximum further from the minimum-sized circuits.

P2Lib: process-portable library and its generation system

This paper describes a process-portable library and its generation system called P2Lib. From technology parameters which characterize a fabrication process, P2Lib generates a complete set of standard cell libraries for logic synthesis, logic simulation, and layout synthesis. A distinctive feature of P2Lib is the rapid characterization of timing and power dissipation by an analytic-oriented method, as well as the accurate characterization by circuit simulation. A designer can quickly create a library under various operating conditions and process specifications, so that he can examine his design with CAD tools. The quality of generated libraries (layout and timing) are discussed and a design example with P2Lib is presented.

An iterative gate sizing approach with accurate delay evaluation

This paper introduces a new gate sizing approach with accurate delay evaluation. The approach solves gate sizing problems by iterating local sizing results from linear programming within mall variable ranges of gate sizes. In each iterative step, variable ranges of gate sizes are updated according to the result from a previous step. Solutions with accurate delay evaluation which consider input signal slopes and separately evaluate rising and falling delays are obtained after several iterative steps. A speedup technique is used to pick out gates actually involved in each local sizing step so as to reduce CPU time. Experiments on sample circuits show that our approach can provide solutions with smaller circuit area than conventional approaches for the same circuit delay or provide solutions under tight delay constraints where conventional approaches can nor reach. Moreover, our approach is faster than the conventional approaches for most circuits, especially under loose delay constraints.

A performance-driven macro-block placer for architectural evaluation of ASIC designs

This paper presents a tool for generating a performance-driven placement from a netlist of Register-Transfer Level (RTL) blocks. Based on the modified force-directed algorithm, the tool chooses locations and orientations of the blocks such a way that to produce a compact area placement with minimum wiring delay along the critical path. Experiments show that our tool (1) provides solutions close to those generated manually, (2) is fast enough to be used in the inner loop of a program that synthesizes RTL structures from behavioral specifications and (3) ensures strong links between RTL synthesis and timing-driven layout so necessary for design of sub-micron ASICs.

A system for analog circuit design that stores and re-uses design procedures

A novel methodology for effective design of analog circuits is presented. While a conventional design environment stores and re-uses designed circuits, the proposed methodology stores a design method that is developed by a designer in his design process, and reuses it for automatic design. In order to evaluate for methodology, an interactive design system called GUIDE has been developed. GUIDE provides a convenient design environment for a designer and automatically stores a design procedure taken in his design process. GUIDE also designs the circuit automatically by reusing the procedure under different sets of specifications and process parameters, which leads to high design efficiency. The effectiveness of the system is demonstrated by experimental results.