Keiko Ariyoshi

3.3-kV-Class 4H-SiC MeV-Implanted UMOSFET With Reduced Gate Oxide Field

A critical issue for SiC trench gate metal-oxide- semiconductor field-effect transistors (UMOSFETs) is gate oxide shielding from the electric field at the trench bottom. In this letter, low ON-resistance with low gate electric field was achieved in a 3.3-kV-class UMOSFET with a unique hexagonal buried p-base region formed by MeV ion implantation. The shielding effect was further enhanced by a self-aligned trench bottom shielding region. The specific ON-resistance, with and without the trench bottom shielding region, was 8.3 and 9.4 mΩcm2, respectively. The blocking voltage in each case was ~3800 V. The electric field in the gate oxide with the trench bottom shielding region was reduced to 2.5 MV/cm at 3300 V.

Determination of optimum structure of 4H-SiC Trench MOSFET

A critical issue for the 4H-SiC UMOSFET is a shielding of the gate oxide at the bottom of the trench gate from the high electric field during the blocking state. This study develops the UMOSFET structure with low specific on-resistance and low electric field in the gate oxide by the two-dimensional numerical device simulation. The gate oxide field is successfully decreased without the degradation of the on-resistance by the structure with the buried p-base region. Furthermore, two-zone Superjunction structure that applies the buried p-base region is also proposed for the 3300 V device.

Threshold Voltage Instability of SiC-MOSFETs on Various Crystal Faces

Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.

14.6 mΩcm2 3.3 kV DIMOSFET on 4H-SiC (000-1)

Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm2 at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm2 to 83.9 mΩcm2 and the threshold voltage decreased from 5.3 V to 3.4 V.

Self-aligned formation of the trench bottom shielding region in 4H-SiC trench gate MOSFET

To suppress the electric field in the gate oxide in a trench gate MOSFET (UMOSFET) with small cell pitch, we developed a technique to form the p+ region using self-aligned ion implantation under the gate trench. To prevent Al+ injection into the trench sidewalls, conditions of thin oxide layer deposition and Al+ implantation were optimized by process simulation. The resulting SiC trench MOS capacitors exhibited long-term reliability, with no degradation in lifetime by the p+ shielding region, and a specific on-resistance of 9.4 mΩ cm2 with a blocking voltage of 3800 V was achieved in the UMOSFET.

Comparative Study of Characteristics of Lateral MOSFETs Fabricated on 4H-SiC (11-20) and (1-100) Faces

We have fabricated the lateral MOSFETs on (11-20) and (1-100) faces and have compared the properties between these faces with various gate oxide processes. It has been demonstrated that (11-20) and (1-100) faces show comparable electrical properties with nitridation treatment on the gate oxide. Our result indicates that both faces exhibit the similar trend of the mobility vs. Dit. Furthermore, it has been shown that NO POA is beneficial to both faces in achieving high channel mobility and suppressed Vt instability.

Systematic investigation on in-plane anisotropy of surface and buried channel mobility of metal-oxide-semiconductor field-effect-transistors on Si-, a-, and m-face 4H-SiC

We have systematically investigated the channel mobility of the 4H-SiC MOSFETs with surface and buried channels in different directions on Si-, a-, and m-faces. We have found that, on a- and m-faces, the in-plane anisotropy of the surface channel mobility is different from that of the buried channel mobility. It has been demonstrated that this anomalous anisotropic behavior can be observed regardless of the gate oxide processes. These results suggest that the dependence of scattering mechanisms or effective masses of carriers on crystal orientations may be modulated near the oxide/SiC interface.

3.3 kV-Class 4H-SiC UMOSFET by Double-Trench with Tilt Angle Ion Implantation

A 3.3 kV trench MOSFET with double-trench structure was demonstrated. The deep buried p-base regions were fabricated using tilt angle ion implantation into the sidewalls of the trench contacts. The distance between the trench gate and trench contact was determined through simulation, in order to optimize the trade-off between on-resistance (RonA) and the electrical field in the oxide (Eox). A tapered trench was located in the connective area between the edge termination and the active area, in order to maintain breakdown voltage. We achieved a RonA of 10.3 mWcm2 and a breakdown voltage of 3843 V and the maximum Eox at breakdown voltage was estimated to be 3.2 MV/cm.

Low Rons in 3kV 4H-SiC UMOSFET with MeV Implanted Buried P-Base Region

3kV UMOSFET with buried p-base regions was developed to realize the low on-resistance with low electric field in the gate oxide for off-state. The buried p-base region was formed simultaneously with the p-base region by utilizing MeV ion implantation. Influence by the structural parameter such as cell geometry and space between the buried p-base region and the trench gate was investigated. The hexagonal cell with high channel density exhibits an extremely low on-resistance of 6.8 mΩcm2 with threshold voltage of 5.0 V at room temperature.

Reliability Improvement and Optimization of Trench Orientation of 4H-SiC Trench-Gate Oxide

Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.