Keishi Tsubaki

A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application

This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparators non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.

A 18.9-nA standby current comparator with adaptive bias current generator

An ultra-low power comparator circuit using adaptive bias current generator (ABCG) is proposed. The circuit consists of an input differential pair, an ABCG, and a latch circuit. The ABCG generates an adaptive bias current, and the latch circuit determines the output logic and controls the operation of the ABCG for ultra-low power dissipation. The ABCG and the latch operate only when the input voltage levels and the logic of the latch do not correspond with each other. Measurements demonstrated that the circuit can achieve highspeed and low-power dissipation due to such operation. The standby current was 18.9 nA with a 10-nA bias current. The power dissipation was 88.5 nW at a 1-kHz input frequency and 3-V supply voltage.

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters

This paper proposes a fully integrated voltage boost converter with a maximum power point tracking (MPPT) circuit for ultra-low power energy harvesting. The converter is based on a conventional charge pump circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient switching operation. The MPPT circuit we propose dissipates nano-watt power to extract maximum power regardless of the harvesters power generation conditions and load current. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input of 0.21 V.

A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator

A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparators non-idealities caused by offset voltage and delay time. We also developed a bias circuit consisting of positive and negative temperature coefficient resistors to obtain the temperature compensated clock frequency. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The power dissipation was 940 nW. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively.

A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters

We propose a fully integrated 3-terminal voltage converter with a maximum power point tracking (MPPT) circuit for ultra-low voltage energy harvesting. The MPPT circuit dissipates nano-watt power to extract maximum output power. The measurement results demonstrated that the circuit converted a 0.49-V input to a 1.46-V output with 73.6% power conversion efficiency when the output power was 348 μW. The circuit can operate at an extremely low input voltage of 0.21 V.

A fully on-chip three-terminal switched-capacitor DC–DC converter for low-voltage CMOS LSIs

In this paper, we present a fully on-chip switched-capacitor DC–DC converter for low-voltage CMOS LSIs. The converter has three terminals of input, ground, and output, by developing control circuits with fully on-chip configuration. We employ an ultra low-power nanoampere bias current and voltage reference circuit to achieve ultra low-power dissipation of control circuits. It enables us to realize a highly efficient power conversion circuit at light-load-current applications. The converter achieves highly efficient and robust voltage conversion using a pulse frequency modulation control circuit and a start-up/fail-safe circuit. Measurement results demonstrated that the converter can convert a 3.0 V input into 1.2 V output successfully. The start-up and fail-safe operations were confirmed through the measurement. The efficiency was more than 50% in the range of 2–6 µA load current.

Nano watt power rail-to-rail CMOS amplifier with adaptive biasing circuits for ultralow-power analog LSIs

In this paper, we present a rail-to-rail folded-cascode amplifier (AMP) with adaptive biasing circuits (ABCs). The circuit uses a nano ampere current reference circuit to achieve ultralow-power and ABCs to achieve high-speed operation. The ABCs are based on conventional circuits and modified to be suitable for rail-to-rail operation. The measurement results demonstrated that the AMP with the proposed ABCs can operate with an ultralow-power of 384 nA when the input voltage was 0.9 V and achieve high speeds of 0.162 V/µs at the rise time and 0.233 V/µs at the fall time when the input pulse frequency and the amplitude were 10 kHz and 1.5 Vpp, respectively.

A low-power single-slope analog-to-digital converter with digital PVT calibration

A low-power single-slope analog-to-digital converter (SS ADC) is presented that uses an ultra-low-power reference current to achieve nano-watt power dissipation and a digital calibration function to compensate for the effect of process, voltage and temperature (PVT) variations. It converts two analog reference voltages into digital reference codes before it converts the input voltage into an input digital code. The SS ADC is tolerant to PVT variations due to the processing of the input digital code and two reference codes in the digital domain. A prototype was fabricated in the 180 nm CMOS process. Measurements demonstrated that it achieved a signal-to-noise-and-distortion ratio of 40.8 dB and an effective number of bits of 6.49 at a sampling rate of 800 S/s. It dissipated 174 nW in analog power and 36.5 nW in digital power, corresponding to the figure of merit for the 293 pJ/conversion-step.

Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems

We propose a sub-1-μs start-up time, fully integrated 32-MHz relaxation oscillator (ROSC) for intermittent VLSI systems. Our proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. The measurement results demonstrated that the ROSC achieved sub-1-μs start-up time and generated stable output frequency of 32.6 MHz. Measured line regulation, temperature coefficient, and variation coefficient in 10 samples were ±0.69, ±0.38, and 0.62%, respectively.

A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems

This paper proposes a fully integrated 32-MHz relaxation oscillator (ROSC) capable of fast start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-μm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-μs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.