Masahiro Numa

1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW.

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

This paper presents a level shifter circuit capable of handling extremely low-voltage inputs. The circuit has a distinctive current generation scheme using a logic error correction circuit that works by detecting the input and output logic levels. The proposed level shifter circuit can convert low-voltage digital input signals into high-voltage digital output signals. The circuit achieves low-power operation because it dissipates operating current only when the input signal changes. Measurement results demonstrated that the circuit can convert a 0.23-V input signal into a 3-V output signal. The power dissipation was 58 nW for a 0.4-V 10-kHz input pulse.

A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities

We have developed a nano-ampere CMOS current reference circuit that is tolerant to threshold voltage variations. This paper describes the circuit and its temperature dependence control technique for ultra-low power LSIs. Because the generated current increases with temperature, we propose a temperature dependence control architecture for a reference current by using the different temperature characteristics of “electron” and “hole” mobilities. Experiment results demonstrated that the circuit can generate a temperature compensated reference current of 9.95 nA and that the temperature dependence of the output reference current can be controlled by using the different temperature dependences of electron and hole mobilities. The temperature dependence controllability was 8.57 pA/˚C·bit and its total current dissipation was 68.1 nA.

A CMOS bandgap and sub-bandgap voltage reference circuits for nanowatt power LSIs

This paper proposes CMOS bandgap reference (BGR) and sub-BGR circuits without resistors for nanowatt power LSIs. The BGR circuit consists of a nano-ampere current reference, a bipolar transistor, and a proportional to absolute temperature (PTAT) voltage generator. The PTAT voltage generator consists of source-coupled differential pairs and generates a positive temperature dependent voltage. The PTAT voltage generator compensates for negative temperature dependence of a base-emitter voltage in a PNP bipolar transistor. The circuit generates a bandgap voltage of silicon. The sub-BGR circuit uses a voltage divider to generate low-voltage sub-bandgap reference. Experimental results demonstrated that the BGR and sub-BGR circuits can generate a 1.18-V and 553-mV reference voltages, respectively. The power dissipation of the BGR and sub-BGR circuits were 108-nW and 110-nW, respectively.

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation

Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active bodybiasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of Vth variation on performance even at ultra low supply voltage less than 0.5 V.

Adaptive arithmetic coding for image prediction errors

This paper presents adaptive arithmetic coding of prediction errors in lossless image compression. Generally, a probability distribution of the errors forms Laplacian distribution with zero mean, but the variance /spl sigma/ of the distribution may take different value at each local area in the image. The proposed encoder estimates the variance /spl sigma/ at every pixel to update the probability table. First, at a target pixel, the variance /spl sigma/ that maximizes the posterior probabilities of neighboring errors is calculated. Next, the error at the target pixel is encoded by arithmetic coding based on probability distribution with the variance /spl sigma/. Since this method calculates the probabilities from fewer neighboring errors, they respond to the rapid changes of image characteristic in narrow area. In this paper, the proposed method is compared with Lempel-Ziv, Huffman, static/adaptive arithmetic coding and JPEG arithmetic coding, and then compression ratios are discussed. On an average, it generates 5% smaller size of compressed data than the adaptive arithmetic method by JPEG.

Leakage power reduction for clock gating scheme on PD-SOI

This paper presents a technique for reducing leakage power of the circuits employing a clock gating scheme on Partially Depleted Silicon On Insulator (PD-SOI). To reduce leakage power while a local clock is disabled, V/sub th/ of each transistor is dynamically controlled by body biasing corresponding to the mode of the local clock. Using PD-SOI is the key to control V/sub th/ within one clock cycle by forward biasing, where V/sub th/ without biasing is designed higher than usual to reduce leakage power. The SPICE simulation results have shown that the proposed technique reduces leakage power by 82% with small area penalty.

A novel power gating scheme with charge recycling

In MTCMOS, the circuit state should be preserved for state retentive sleep, and the virtual power/ground rails clamp (VRC) scheme is an effective method for this purpose. Our approach realizes the voltage clamp function without additional devices like diodes, by feeding the virtual ground voltage back into a sleep signal. There are also other effects; cutting off the leak current of the sleep buffer, and charge recycling of sleep signal node. We have achieved a 19.7% lower power consumption and a 5.4% cell area reduction.

A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application

This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparators non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.

A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs

In this paper, we propose a low-power level shifter (LS) capable of converting extremely low-input voltage into high-output voltage. The proposed LS consists of a pre-amplifier with a logic error correction circuit and an output latch stage. The pre-amplifier generates complementary amplified signals, and the latch stage converts them into full-swing output signals. Simulated results demonstrated that the proposed LS in a 0.18-μm CMOS process can convert a 0.19-V input into 1.8-V output correctly. The energy and the delay time of the proposed LS were 0.24 pJ and 21.4 ns when the low supply voltage, high supply voltage, and the input pulse frequency, were 0.4, 1.8 V, and 100 kHz, respectively.