Keisuke Shinohara

Extremely High gm> 2.2 S/mm and fT> 550 GHz in 30-nm Enhancement-Mode InP-HEMTs with Pt/Mo/Ti/Pt/Au Buried Gate

We have successfully developed 30-nm enhancement-mode (E-mode) InGaAs/InAlAs high electron mobility transistors (HEMTs) with an extremely high transconductance (gm ) of 2.22 S/mm, a current gain cutoff frequency (fT) of 554 GHz, and a maximum oscillation frequency (fmax ) of 358 GHz. The excellent high-speed performance was obtained by using a Pt/Mo/ Ti/Pt/Au buried gate technology, which enabled E-mode operation for very short 30-nm HEMTs while maintaining a low access resistance as well as a low gate leakage current. The effectively short gate-to-channel distance suppressed the short channel effect, resulting in a very high gm independent of the gate length (Lg ) and a greatly reduced output conductance (gd).

Ultra-High-Speed Low-Noise InP-HEMT Technology

InP-based high electron mobility transistors (InP-HEMTs) with an ultra-high current gain cutoff frequency (fT) of over 550 GHz and a maximum oscillation frequency (fmax) of 500 GHz are realized. The excellent performance is achieved through lateral and/or vertical device scaling in combination with a reduction of parasitic resistances and capacitances. Key device technologies for ultra-high-speed, low-noise performance are described

InP DHBT IC Technology with Implanted Collector Pedestal and Electroplated Device Contacts

The authors report an InP DHBT IC technology that incorporates an ion implanted N+ collector-pedestal for collector-base capacitance (C cb) reduction. The technology utilizes electroplating processes and sidewall spacers to form a high yield self-aligned base-emitter junction. Devices with 0.4 mum emitter junction widths demonstrate peak ft and fmax values of over 370 GHz. The devices demonstrate a ~35% reduction in Ccb versus HBTs with the same device footprint fabricated without a collector pedestal. A current mode logic (CML) divide-by-two circuit demonstrated a maximum operating frequency of 128 GHz, a -20% improvement versus the same design realized in a non-collector-pedestal process

Developing Bipolar Transistors for Sub-mm-Wave Amplifiers and Next-Generation (300 GHz) Digital Circuits

Here we consider the prospects for continued improvement in InP HBTs, specifically the challenges faced in a further doubling of transistor and IC bandwidth. Our objective is an IC technology supporting 300 GHz digital clock rates, -600 GHz reactively-tuned amplifiers, and balanced cutoff frequencies in the 700-1000 GHz range. Such ICs would permit monolithic transceivers for 300 GHz and 600 GHz imaging systems, -250 GHz high-rate communications radios, chip sets for 300 Gb/s optical data transmission, and very high-resolution microwave mixed-signal ICs.

An Ultra Low-Power (⩽13.6 mW/latch) Static Frequency Divider in an InP/InGaAs DHBT Technology

An ultra-low power static frequency divider with a maximum clock frequency > 61 GHz was designed and fabricated into a 500 nm InP/In 0.53Ga47As/InP double heterojunction bipolar transistor (DHBT) technology utilizing a collector pedestal process for reduced base-collector capacitance Ccb. This is the first reported digital circuit in this material system employing such Ccb reduction techniques. The divider operation is fully static, operating from fclk = 4 GHz to 61.2 GHz while dissipating 27.1 mW of power in the flip-flop from a single -2.30 V supply. The power-delay product of this circuit is 113.0 fJ/latch if all devices in the latch are considered and 63.2 fJ/latch if the power associated with the voltage level-shifting emitter followers is not included in the power-delay calculation. By either method of calculation, this is a record low power-delay product for an InP DHBT-based static frequency divider; more than 2times lower than has been previously reported. The circuit employs the current mode logic (CML) topology and inductive peaking

Selectively Implanted Subcollector DHBTs

In_0.53Ga_0.47As/InP double heterojunction bipolar transistors with implanted subcollectors have been designed and fabricated to eliminate the base access pad capacitance. A blanket Fe implant eliminates the interface charge and a patterned Si implant creates an isolated N⁺⁺ subcollector. The extrinsic base-collector capacitance C_cb associated with the base interconnect pad (-25% of the total C_cb) is thus eliminated. These implanted subcollector DHBTs have 363 GHz f_t and 410 GHz f_max. The DC current gain beta ~ 40, BV_ceo = 5.6 V, BV_cbo = 6.9 V (Ic = 1 mA)

Interface charge compensation in InP based heterojunction bipolar transistors with implanted subcollectors

We report InP∕In0.53Ga0.47As∕InP double heterojunction bipolar transistors (DHBTs) with implanted subcollectors. We demonstrate the compensation of charge at the regrowth interface by the use of a blanket Fe implant. An isolated N++ subcollector is then formed by a patterned Si implant. With the compensation of the interface charge, this patterned subcollector eliminates the extrinsic base-collector capacitance Ccb associated with the base interconnect pad over the entire range of bias voltages. These implanted subcollector DHBTs with the shallow Fe implant have 363GHz fτ and 410GHz fmax. The dc current gain β∼40, BVceo=4.9V, BVcbo=5.4V, and Icbo<70pA at Vcb=0.3V.

Vertically-scaled 100nm T-gate AlGaN/GaN HEMTs with 125GHz f/sub T/ and 174GHz f/sub MAX/

In this work, we report on vertically scaled, 100nm gate-length Al _0.31Ga_0.69N/AlN/GaN HEMTs with a low sheet resistance of 260Omega/square, an f_T of 125 GHz and an f _max (U_g) of 174 GHz. Careful device design and unique process features also resulted in a high peak G_m,ext of 498 mS/mm, an I_dss of 1.2A/mm, and a gate-to-drain breakdown of 30V