Petra Rowell

InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz

We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.

130nm InP DHBTs with ft >0.52THz and f max >1.1THz

We report results from a 130nm Indium Phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A 0.13×2µm² transistor exhibits a current gain cutoff frequency ft >520GHz, with a simultaneous extrapolated power gain cutoff frequency f<inf>max</inf>>1.1THz. The HBTs exhibit these RF figures-of-merit while maintaining a common-emitter breakdown voltage BV<inf>CEO</inf>=3.5V (J<inf>E</inf>=10µA/µm²). Additionally, scaling of the emitter junction length to 2µm enables high device performance at low total power levels. Transistors in the InGaAs/InP material system have demonstrated the highest reported transistor RF figures-of-merit. Previous published results include strained-InGaAs channel high-electron mobility transistors (HEMTs) with f<inf>max</inf> of >1THz [1,2], and InP DHBTs with f<inf>max</inf> >800GHz [3]. High bandwidth DHBTs have applications in a number of RF and mixed-signal applications due to their high power handling and high levels of integration relative to HEMTs. The HBTs reported in this work are designed for transceiver applications at the lower end of the THz frequency band [0.3–3 THz].

InP HBT Integrated Circuit Technology for Terahertz Frequencies

We report on the development of an InP DHBT integrated circuit technology for applications at the lower range of the THz frequency band (0.3-3 THz) 0.25um HBTs demonstrate an extrapolated fmax of >800GHz while maintaining a common-emitter breakdown voltage of >4V. The transistors have been integrated a full IC process that includes three-levels of interconnects, backside wafer thinning to 50um with a through-wafer via process, and a backside etch singulation process that allows for the formation of free standing integrated waveguide probes. The technology has been utilized to demonstrate amplifiers, oscillators and dynamic frequency dividers all operating at >300GHz.

Transistor and circuit design for 100-200 GHz ICs

Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f/sub /spl tau// and 490 GHz f/sub max/ DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C/sub cb/, and emitter junction regrowth for reduced base and emitter resistances.

g300GHz fixed-frequency and voltage-controlled fundamental oscillators in an InP DHBT process

We report fundamental fixed-frequency and voltage-controlled oscillators operating at >300GHz fabricated in a 256nm InP DHBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer. Measured oscillation frequencies of fixed-frequency designs are 267.4, 286.8, 310.2, and 346.2GHz, at P<inf>DC</inf>=35mW. At optimum bias, the output power was measured to be −5.1, −6.9, −9.2, and −11.0 dBm for each design (no probe loss correction), with P<inf>DC</inf>≤115mW. Measured phase noise was −96.6dBc/Hz at 10MHz offset. Varactor-tuned designs demonstrated 10.6–12.3 GHz of tuning bandwidth.

Ultra high frequency static dividers > 150 GHz in a narrow mesa InGaAs/InP DHBT technology

A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In/sub 0.53/Ga/sub 0.47/As/InP DHBT technology. The divider operation is fully static, operating from f/sub dk/ = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 /spl mu/m and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.

A 220 GHz InP HBT Solid-State Power Amplifier MMIC with 90mW POUT at 8.2dB Compressed Gain

A 220 GHz Solid State Power Amplifer MMIC is presented simultaneously demonstrating 90mW output power Pout and 8.2dB compressed gain. This 2-Stage, 8-Cell amplifier has 14.8 dB S21 gain at 220GHz, with small signal bandwidth from at least 190 to 240GHz. PDC is 4.46W. Amplifier cells were fabricated from a 250nm InP HBT technology, jointly with a substrate- shielded, thin-film microstrip wiring environment using BCB. The 90mW Pout is achieved by combining eight amplifier cascode cells. The use of two gain stages relaxes the RF source power demands, where only 13.6mW Pin is needed to achieve 90mW Pout. Over 10GHz bandwidth, at least 75mW Pout is observed from 210 to 220GHz.

Deep submicron InP DHBT technology with electroplated emitter and base contacts

We report the development of a wide bandwidth InP double heterojunction bipolar transistor technology that utilizes novel electroplating processes to form the emitter and base contacts. The technology enables the fabrication of HBTs with deep submicron emitter-base junction dimensions and self-aligned base ohmic contacts. Using this technology, HBTs have been fabricated with emitter junction widths scaled to 0.25 /spl mu/m. These devices demonstrated peak f/sub /spl tau// and f/sub max/, values of over 300 GHz. The transistors also support high current density operation (J/sub E/>7 mA//spl mu/m/sup 2/) and have a low collector-base capacitance to collector current ratio (C/sub cb//I/sub c//spl sim/0.55 ps/V), an important parameter for digital logic speed.

Advanced InP DHBT process for high speed LSI circuits

We report on the development of an advanced InP double heterojunction bipolar transistor (DHBT) technology that utilizes electroplated device contacts and dielectric sidewall spacers to form a self-aligned base-emitter junction. These processes permit aggressive scaling of the transistor, while achieving high levels of yield and manufacturability. HBTs with 0.5 mum emitter junction widths have been demonstrated with an ft/fmax of 405/390 GHz and a common-emitter breakdown voltage BVCEO >4 V. Large-scale direct digital synthesizer (DDS) circuits have been fabricated operating at clock rates up to 24 GHz.

Multi-finger 250nm InP HBTs for 220GHz mm-wave power

We present here measured DC and RF performance of multi-finger 250nm InP HBTs intended for power amplifier design at high-mm, sub-mm-wave frequencies. The designs presented are in common-emitter and common-base configuration, having 24um periphery. Performance limitations for the PA cell have been identified and mitigated through novel design and layout - they include HBT thermal impedance, RF bandwidths ft and fmax, MAG/MSG @ 220GHz, and reduced common-base stability from parasitic base inductance Lb and/or collector-emitter capacitance Cce. The PA cells are realized using substrate-shielded non-inverted thin-film microstrip wiring to minimize Lb and Cce, make small the feed lines to the multi-finger devices, and prevent parasitic substrate-mode excitation in the 12.8-εr InP substrate.