Keith F. Beckham

Flip-chip interconnection technology for advanced thermal conduction modules

Area array solder bumps on silicon devices, known as C4 balls, have been successfully used in terminating logic and memory devices to ceramic substrates in numerous IBM products over two decades. With the IBM System 390/ES9000 series of mainframe computers, this highly reliable chip termination technology has achieved improved interconnection density and total number of chip I/O connections per module. In addition, in the models 820 and 900 of ES9000 series, a novel materials set, namely glass-ceramic with Cu internal metallization along with thin-film redistribution wiring on top, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules which also have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70000 solder balls per module is discussed.<<ETX>>

Device interconnection technology for advanced thermal conduction modules

The use of area array solder bumps on silicon devices known as controlled collapse chip connection (C4) balls for terminating logic and memory devices to ceramic substrates has been extended in both interconnection density and total number of chip I/O connections per module. In addition, a novel materials set, namely glass-ceramic with copper internal metallization along with thin film redistribution wiring on the top surface, has been introduced for multilayered ceramic substrates. Key elements of advanced glass-ceramic substrate technology relevant to flip-chip joining are reviewed. This is followed by a discussion of device join and replace processes used in advanced thermal conduction modules (ATCMs). These models have decoupling capacitors which are attached by C4 solder reflow. Optimization of the top surface metallurgy and device join parameters necessary to achieve reliable joining of more than 70,000 solder balls per module is discussed. >

Electrical connections to the thermal conduction modules of the IBM Enterprise System/9000 water-cooled processors

In a complex multichip carrier such as the thermal conduction module (TCM) of IBM high-performance mainframe processors, the interfaces between chips and their substrate as well as between the substrate and its printed circuit board must support a large number of electrical connections. Since chip, substrate, and board typically comprise very different materials, the electrical connections between them must be able to accommodate considerable thermally induced mechanical stress during assembly and use. This paper describes the pin attachment, chip attachment. wire bonding, and laser deletion processes used for forming the electrical connections to theglass-ceramic/copper/polyimide/copper substrate of the thermal conduction modules of the IBM Enterprise System/9000TM watercooled processors.

Evaluation of back end of line structures underneath wirebond pads in ultra low-k device

Mechanical integrity of back end of line structures underneath wirebond pads was evaluated using 32 nm ultra low-k device by wire pull testing and 3D finite element analysis. Pad tearout rate at wire pull testing was measured for various Cu line/via structures. One key factor for robust bond pads is effective modulus in ULK levels. In addition, increased via and wiring metal density reduces the risk of pad tearout. For the evaluated structures in this work, a calculated effective modulus in ULK was a better index than metal layout type for assessment of bond pad robustness in cooperation with finite element analysis data. Wirebonding is another key factor affecting pad tearout. In this work, effects of wirebond geometry (i.e. wire size and bond ball size) on pad tearout were focused rather than the effect of parameter itself. With the robust BEOL stack and appropriate wirebonding conditions, module level reliability of 35 μm ultra fine pitch wirebond on ultra low-k chip with circuit underneath bond pads was also demonstrated with a PBGA package.